Ze Hong Zhang

Basal plane dislocation-free epitaxy of silicon carbide

Molten KOH etching was implemented on SiC substrates before growing epilayers on them. It was found that the creation of basal plane dislocation (BPD) etch pits on the substrates can greatly enhance the conversion of BPDs to threading edge dislocations during epitaxy, and thus low BPD density and BPD-free SiC epilayers are obtained by this method. The reason why BPD etch pits can promote the earlier conversion is discussed. The SiC epilayer growth by this method is very promising in overcoming forward voltage drop degradation of SiC PiN diodes.

Mechanism of eliminating basal plane dislocations in SiC thin films by epitaxy on an etched substrate

Homoepitaxial growth is performed on 8° off-axis SiC substrates that are molten KOH etched. The shape of a basal plane dislocation (BPD) etch pit at different stages of epitaxial growth is studied by atomic force microscopy. It is found that the growth steps covering a BPD etch pit are curved, and both the usual step-flow growth and lateral growth perpendicular to the step-flow direction will take place in the pit simultaneously during epitaxy. The lateral growth is usually dominant and “blocks” the path for the BPD to propagate, and thus the conversion of BPDs to threading edge dislocations is enhanced.

Evolution of basal plane dislocations during 4H-silicon carbide homoepitaxy

A method based on the combination of molten KOH etching and reactive ion etching was developed to track dislocations from 4H-silicon carbide homoepilayer to the substrate. The conversion of basal plane dislocations (BPDs) to threading edge dislocations (TEDs) was found to occur at the epilayer/substrate interface. The BPDs with dislocation lines parallel (or approximately parallel) to the off-cut direction may propagate as BPDs into the epilayer, while those with dislocation lines forming large angles (>10°) with the off-cut direction will get converted to TEDs. A model is proposed to explain the observations.

Delineating Structural Defects in Highly Doped n-Type 4H-SiC Substrates Using a Combination of Thermal Diffusion and Molten KOH Etching

Delineation of structural defects by molten KOH etching is not satisfactory for highly doped n-type Si-face SiC substrates. This difficulty was overcome by converting the substrates to p-type via diffusion of boron, followed by molten KOH etching. Three kinds of typical etch pits were clearly distinguished, corresponding to elementary screw, threading edge, and basal plane dislocations. Comparison of molten KOH etching effects on 4H-SiC samples of different types indicates that molten KOH etching is a combination of chemical and electrochemical processes, during which the preferential and isotropic etchings are competitive, depending on the SiC conductivity type and doping concentration.

The Effect of Doping Concentration and Conductivity Type on Preferential Etching of 4H-SiC by Molten KOH

Molten KOH etchings were implemented to delineate structural defects in the n- and ptype 4H-SiC samples with different doping concentrations. It was observed that the etch preference is significantly influenced by both the doping concentrations and the conductivity types. The p-type Si-face 4H-SiC substrate has the most preferential etching property, while it is least for n + samples. It has been clearly demonstrated that the molten KOH etching process involves both chemical and electrochemical processes, during which isotropic etching and preferential etching are competitive. The n + 4H-SiC substrate was overcompensated via thermal diffusion of boron to p-type and followed by molten KOH etching. Three kinds of etch pits corresponding to threading screw, threading edge, and basal plane dislocations are distinguishably revealed. The same approach was also successfully employed in delineating structural defects in (000 1 ) C-face SiC wafers.

Propagation of stacking faults from surface damage in SiC PiN diodes

The propagation of stacking faults (SF) in SiC PiN diodes under forward bias was studied by the electron beam induced current mode of scanning electron microscopy. The primary SF nucleation sites were confirmed to be pre-existing basal plane dislocations (BPD). Damage to the diode surface can also cause SF propagation in the device. Hence, in addition to the elimination of BPDs in the active layer of the diode, avoidance of surface damage by paying careful attention to device processing and testing is also important for fabricating stable SiC PiN diodes.

Why Are Only Some Basal Plane Dislocations Converted to Threading Edge Dislocations During SiC Epitaxy

Dislocations were tracked from 4H-SiC epilayer to the substrate by a new method based on combination of molten KOH etching and Reactive Ion Etching. It was found that basal plane dislocations (BPDs) with dislocation lines parallel (or approximately parallel) to the off-cut direction might propagate as BPDs into the epilayer, while those with dislocation lines forming large angles (>10º) with the off-cut direction will get converted to threading edge dislocations (TEDs). A model is proposed to explain the observations.

Growth of Low Basal Plane Dislocation Density SiC Epitaxial Layers

A method was developed in our laboratory to grow low basal plane dislocation (BPD) density and BPD-free SiC epilayers. The key approach is to subject the SiC substrates to defect preferential etching, followed by conventional epitaxial growth. It was found that the creation of BPD etch pits on the substrates can greatly enhance the conversion of BPDs to threading edge dislocations (TEDs) during epitaxy, and thus low BPD density and BPD-free SiC epilayers are obtained. The reason why BPD etch pits can promote the above conversion is discussed. The SiC epilayer growth by this method is very promising in overcoming forward voltage drop degradation of SiC PiN diodes.

CVD Growth and Characterization of 4H-SiC Epitaxial Film on (11-20) As-Cut Substrates

Thick epilayers up to 60 µm have been grown on ) 0 2 11 ( face SiC substrates at a growth rate of 15 µm/hr by chemical vapor deposition (CVD). The epilayer surface is extremely smooth with a RMS roughness of 0.6 nm for a 20µm×20µm area. Threading screw and edge dislocations parallel to the c-axis are present in the ) 0 2 11 ( substrate; however, they do not propagate into the epilayer. The I-V characteristics of the Schottky diodes on this face were studied. Basal plane (0001) dislocations with a density of ~105 cm-2 were found in the ) 0 2 11 ( epilayers by molten KOH etching and electron beam induced current (EBIC) mode of the scanning electron microscope (SEM).

Performance of silicon carbide PiN diodes fabricated on basal plane dislocation-free epilayers

The nucleation sites of stacking faults (SFs) during forward current stress operation of 4H-SiC PiN diodes were investigated by the electron beam induced current (EBIC) mode of scanning electron microscopy (SEM), and the primary SF nucleation sites were found to be basal plane dislocations (BPDs). Damage created on the diode surface also acts as SF nucleation sites. By using a novel BPD-free SiC epilayer, and avoiding surface damage, PiN diodes were fabricated which did not exhibit SF formation under current stressing at 200A/cm2 for 3 hours.