Arul Chakkaravarthi Arjunan
University of Florida
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Publication
Featured researches published by Arul Chakkaravarthi Arjunan.
Electrochemical and Solid State Letters | 2009
Purushottam Kumar; S. Y. Son; Jaeseok Lee; Feng-Chi Chang; Aniruddh Khanna; Arul Chakkaravarthi Arjunan; Rajiv K. Singh
Chemical mechanical polishing (CMP) was used to shape hexagonally arranged 20 μm diam cone-shaped structures, prepared by wet etching of Coming 2496 glass, into microlenses. Edge rounding, which occurs during CMP due to a higher removal rate at the edges, was utilized for shaping of the microlenses. Microlenses with an H/D ratio of ∼ 1/10 and radius of curvature of 27.5 μm were obtained. CMP variables that affect the contact pressure and material removal rate are downpressure, linear velocity, slurry, and properties of the pad. These variables being external to substrate provide great flexibility and, hence, suitability of the process for a wide range of materials.
Applied Physics Letters | 2018
J. Kim; Jongsik Kim; Yan Xin; Jinhyung Lee; Young Gyun Kim; Ghatu Subhash; Rajiv K. Singh; Arul Chakkaravarthi Arjunan; Haigun Lee
The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (∼3u2009nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.
Archive | 2011
Rajiv K. Singh; Arul Chakkaravarthi Arjunan; Deepika Singh
Archive | 2010
Rajiv K. Singh; Arul Chakkaravarthi Arjunan; Dibakar Das; Deepika Singh; Abhudaya Mishra; Tanjore V. Jayaraman
Archive | 2010
Rajiv K. Singh; Purushottam Kumar; Deepika Singh; Arul Chakkaravarthi Arjunan
Thin Solid Films | 2009
Sushant Gupta; Arul Chakkaravarthi Arjunan; Sameer Deshpande; Sudipta Seal; Deepika Singh; Rajiv K. Singh
Applied Surface Science | 2008
Arul Chakkaravarthi Arjunan; Deepika Singh; Hung-Ta Wang; F. Ren; Purushottam Kumar; Rajiv K. Singh; S. J. Pearton
Archive | 2011
Rajiv K. Singh; Arul Chakkaravarthi Arjunan; Deepika Singh; Abhudaya Mishra
Electrochemical and Solid State Letters | 2012
Arul Chakkaravarthi Arjunan; Kannan Balasundaram; Purushottam Kumar; Jaeseok Lee; Sang Hyun Yoon; S.D. Kim; Sushant Gupta; Rajiv K. Singh
Archive | 2012
Rajiv K. Singh; Deepika Singh; Arul Chakkaravarthi Arjunan