Zehong Li

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

A high-voltage lateral double-diffusion MOSFET (LDMOS) with a charge-balanced surface low on-resistance path (CBSLOP) layer is proposed and experimentally demonstrated using a modified CMOS process. The CBSLOP layer can not only provide a low on-resistance path in the on-state but also keep the charge balance between the N and P pillars of a surface low on-resistance path in the off-state, which results in improved breakdown voltage (BV). The experimental results show that the CBSLOP-LDMOS with a drift length of 35 mum exhibits a BV of 500 V and specific on-resistance (<i>R</i> _on, _sp) of 96 mOmega ldr cm², yielding to a power figure of merit (<i>BV</i> ²/ <i>R</i> _on, _sp) of 2.6 MW/cm² . The excellent device performances, coupled with a CMOS-compatible fabrication process, make the proposed CBSLOP-LDMOS a promising candidate for smart power integrated circuit.

A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS

Integrated in a 0.35 μm 700 V BCD process platform, ultra-low R_{on, sp} 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which R_{on, sp} are 11.5 Ω·mm² and 11.2 Ω·mm², respectively. Utra-low R_{on, sp} benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around birds beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.

Equivalent Substrate Model for Lateral Super Junction Device

The equivalent substrate (ES) model and the accordant optimized structure for the lateral super junction (LSJ) device are proposed in this paper. The ES, defined as the combination of the depleted substrate under the reverse voltage and the charge compensation layer (CCL) in the substrate, is treated as a whole to analyze the modulation impact of the compensation electric field ΔE on the total electric field of the LSJ. The analytical formulas for the surface electric field profiles of the LSJ are deduced from the 3-D Poisson equation and the Green function. The ES model reveals the essence and the suppression of the substrate-assisted depletion effect in the LSJ, from which the optimized substrate conditions are achieved. The optimized substrate condition allows the LSJ device featuring a similar breakdown voltage to that of the vertical super junction. Then four typical doping concentrations of the CCLs with four different compensation electric field strengths ΔEs are compared. The developed novel device with optimized CCL delivers a breakdown voltage of 301 V, realizing 157% improvement compared with the conventional LSJ with Ld=15 μm, which shows a superior performance to the LSJ devices reported. It is noteworthy that the ES model can also be used to analyze other LSJs.

The Rule of Field Enhancement for Buried Dielectric Layer of SOI High Voltage Devices

Based on the concept of critical field E_I,C approaching for dielectric layer, the ENDIF (ENhanced Dielectric layer Field) principle for SOI HV devices is proposed for the first time, from which three approaches to enhance field of dielectric layer E_I for increasing vertical breakdown voltage V_B,v are presented: (1) enhance the critical field in silicon E_S,C at the interface of Si/dielectric layer by using thin silicon layer. Considering the threshold energy of silicon E_T, the expression of E_S,C for both thick and thin Si layer is derived firstly and shown that E_S,C increases sharply with decreasing of thin Si layer thickness t_s and E_S,C and E_I for SiO₂ are up to 141V /mum and 422 V /mum at t_s = 0.1mum, respectively; (2) raise a structure of buried dielectrics layer with low permittivity (LK) and variable permittivity (VK) (3) implement the interface charges between silicon and dielectric layer, from which a new dielectric structure with DT SOI is proposed, and E_I of 300 V/mum is experimentally obtained. By ENDIF, the formula E_I and V_B,V are given, which are meet good with 2D simulation and experimental results. With ENDIF, several conventional SOI devices are well explained.

A high reliable reverse-conducting IGBT with a floating P-plug

A current distribution model is presented for the RC-IGBTs both at IGBT mode and DIODE mode. According to the analytical model, smaller cell size would be better for the distribution of the current density and full utilization of the silicon, but the snapback would be worse. Then a novel RC-IGBT with a floating P-plug is proposed and investigated by simulations. The results show that it can suppress the snapback phenomena effectively. More importantly, the silicon utilization ratio is much higher than the others RC-IGBTs and the current is uniformly distributed in the whole wafer both at IGBT mode and DIODE mode that ensured the high temperature reliability of the RC-IGBT.

Design and Optimization of a Versatile 700 V SPIC Process Using a Fully Implanted Triple-well Technology

A SPIC (smart power IC) process with a wide range of devices up to 700 V has been designed and optimized. An important feature is that all the devices have been realized by using a fully implanted triple-well technology in a P-type single crystal without epitaxial layer or buried layer. The results of this process are the low fabrication cost, simple process and small chip area. In addition to high voltage lateral DMOS (HV-LDMOS) transistor with the breakdown voltage (BV) 700 V as well as JFET device and low voltage CMOS (LV-CMOS) transistors have been fabricated using this process, a NPN type bipolar transistor is also realized and optimized by a additional implantation and drive-in. The major features of this process for SPIC fabrication have been clearly demonstrated

Theory of Superjunction With NFD and FD Modes Based on Normalized Breakdown Voltage

A new relationship between the specific ON-resistance R_ON and breakdown voltage V_B for the balanced symmetric superjunction (SJ) device is presented to produce the lowest R_ON for a given V_B. The design formulas, including the doping density NW and the drift length L_d, are given for both the nonfull depletion (NFD) and the full depletion SJ devices with an introduction of the normalized V_B factor η. For the NFD SJ MOSFET, an R_ON ∝ V1.03 B relationship is obtained. The analytical results show good agreement with the numerical results.

Optimization of Lateral Superjunction Based on the Minimum Specific ON-Resistance

The optimization methodology of the minimum specific ON-resistance RON,min for the lateral superjunction device is proposed based on the concepts of charge and potential electric fields in this paper. From the RON,min method, a new relationship between RON and breakdown voltage VB is developed, and the analytical formulas are obtained to directly give the doping concentration N and the drift length Ld. The calculated results, including the 800 and 1600 V examples, are in good agreement with the simulations. The optimized designs are also compared with the existing experimental and simulated data. It is shown that RON from the proposed optimization method is minimum, and the methodology of RON,min is universal.

New Lateral IGBT with Controlled Anode on SOI substrate for PDP scan driver IC

A new Lateral Insulated-Gate Bipolar Transistor (LIGBT) structure on SOI substrate, called Controlled Anode LIGBT (CA-LIGBT), is proposed. The design of the new structure results in high breakdown voltage and good trade off between turn-off time and on-state voltage drop. Simulation results show that the CA-LIGBT has about 85.0% reduction in turn-off time and about 20.0% increase in on-state voltage drop, as compared to the conventional LIGBT. The breakdown voltage is above 200V. The proposed SOI CA-LIGBT can be fabricated by the conventional trench SOI power ICs process steps, and it is useful for PDP scan driver IC.

The

The global optimization of the balanced symmetric vertical superjunction (VSJ) device is proposed based on the R-well model for the first time to realize the unique minimum specific on-resistance R_ON,min. The R-well model, which is originated from our previous VSJ mode theory, shows the relationship between R_ON and the doping concentration N under the given pillar width W and breakdown voltage V_B. The global R_ON optimization is realized to obtain the design formulas of N and the pillar length Ld. The calculated results are in good agreement with the simulations. It is demonstrated from the comparisons with the simulations and the existing experiments that the optimization in this paper realizes the unique R_on,min with a relationship of R_ON ∝ V_B^1.03. The R-well model is also universal for other R_on optimizations.