Zhan Chai

A Tunnel Diode Body Contact Structure to Suppress the Floating-Body Effect in Partially Depleted SOI MOSFETs

A novel SOI MOSFET structure to suppress the floating-body effect (FBE) and the short-channel effects is proposed and successfully demonstrated. In the new structure, a tunnel diode body contact is embedded in the source region, which can effectively release the accumulated body carriers. In an nMOSFET, a heavily doped p+ layer is introduced beneath the n+ source region so that the body and the source are effectively connected through tunneling. The fabricated device shows the suppressed FBE and lower DIBL. The new structure does not enlarge the device size and is fully compatible with SOI CMOS technology.

A Tunnel Diode Body Contact Structure for High-Performance SOI MOSFETs

A tunnel diode body contact (TDBC) silicon-on-insulator (SOI) MOSFET structure without floating-body effects (FBEs) is proposed and successfully demonstrated. The key idea of the proposed structure is that a tunnel diode is embedded in the source region, so that the accumulated carriers can be released through tunneling. In an n-MOSFET, a heavily doped p+ layer is introduced beneath the n+ source region. The simulated and measured results show the suppressed FBE, as expected. Other phenomena that originate from the FBEs, such as the kink, linear kink effect, abnormal subthreshold swing, and small drain-tosource breakdown voltage in the properties, were also sufficiently suppressed. In addition, it should be noted that the proposed SOI MOSFETs are fully laid out and process compatible with SOI CMOS. Hysteresis effects disappear in TDBC SOI MOSFETs, which makes them attractive for digital applications. On the other hand, in analog applications, TDBC SOI MOSFETs are shown to hold the advantage over floating-body SOI MOSFETs due to their higher Gm/ID ratio. TDBC SOI MOSFETs can be considered as one of the promising candidates for digital and analog devices.

Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories

A capacitorless DRAM cell, floating-body/gate cell (FBGC), is experimentally presented with planar partially depleted SOI CMOS technology. The specially designed gate/drain underlap and gate/source overlap of the first transistor enable long worst case retention time as well as the fast write speed. The operation power dissipation is dramatically reduced while maintaining high sense margin. In addition, FBGC demonstrates excellent endurance performance and nondestructive read operation.

Temperature Dependence of Hysteresis Effect in Partially Depleted Silicon-on-Insulator MOSFETs

The hysteresis effect on the output characteristics, which originates from the floating-body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs, at different temperatures between 25 °C and 125 °C. For a better understanding of the hysteresis characteristics, the authors developed ID hysteresis which is defined as the difference between ID versus VD forward sweep and reverse sweep. The fabricated devices show positive and negative peaks in Id hysteresis. The experimental results show that ID hysteresis declined as the operating temperature increases. Based on the measurement, we have demonstrated the temperature dependence of hysteresis effect in PD SOI MOSFETs.

Total Dose Effects in Tunnel-Diode Body-Contact SOI

Tunnel-Diode Body-Contact (TDBC) SOI MOSFETs utilize a shallow source and a deep drain to eliminate total-ionizing-dose induced back-channel leakage and to suppress floating body effects. In contrast, significant leakage current is observed in T-gate Body-Contact (TB) SOI nMOSFETs, as a result of trapped charge in the buried oxide. A subthreshold hump is observed in TDBC SOI nMOSFETs after irradiation. The charge trapped at the shallow trench isolation (STI) corner is the major reason for the post-irradiation hump in the current-voltage characteristics. Pocket p+ implantation reduces the size of the subthreshold hump in short-channel TDBC devices.

n

Radio-frequency (RF) performance of multi-finger partially depleted silicon-on-insulator (SoI) nMOSFETs with tunnel diode body contact (TDBC) structure is investigated in this letter. The TDBC structure suppresses floating-body effect and body instability significantly and shows less drain conductance degradation with respect to FB and TB devices. The peak cutoff frequency (fT) and maximum oscillation frequency (fMAX) of TDBC devices are 96.4 and 132.8 GHz, respectively. Due to lower parasitic resistances and capacitances, the device with TDBC structures represents an improvement of 10% for the fT and of 90% for the fMAX compared with conventional T-gate body-contact devices. The investigation results indicate that TDBC SoI MOSFETs are a good candidate for analog and RF applications.

MOSFETs

On the basis of a detailed discussion of the development of total ionizing dose (TID) effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.

Improvement of RF Performance by Using Tunnel Diode Body Contact Structure in PD SOI nMOSFETs

Single-event transient (SET) responses are compared for floating-body contact, T-gate body-contact (TB), and tunnel-diode body-contact (TDBC) silicon-on-insulator (SOI) MOSFETs. The influence of three body-contact schemes on SET sensitivity is examined via irradiations as functions of position, bias voltage, and device size. The mechanisms of SET in SOI devices are discussed. Although both TB and TDBC schemes suppress floating body effects (FBEs), the TDBC scheme has superior SET hardness because it effectively eliminates charge enhancement due to bipolar amplification originating from FBEs. Thus, TDBC-structure SOI devices can lead to improved single-event upset hardness in static random access memory cells.

New Method of Total Ionizing Dose Compact Modeling in Partially Depleted Silicon-on-Insulator MOSFETs

Tunnel diode body contact (TDBC) MOSFETs is used to suppress floating body effects (FBE) and achieve significant improvement in RF performance. For the first time, low frequency noise (LF noise) of TDBC MOSFETs, also called 1/f noise, is reported in this paper. LF noise performance of floating body (FB), T-gate body contact (TB) and TDBC MOSFET fabricated in 0.13 μm Smart-Cut partially depleted (PD) SOI technology is compared. Excess Lorentzian noise caused by ionization impact under high drain voltage is observed in FB devices. Due to tunnel diode embedded beneath the source region, carries in body region is released by quantum tunneling effect, floating body effects and noise overshot phenomenon are suppressed as well as TB device. The results indicate that TDBC device has a comparable LF noise performance as TB device and is suitable for RF application.

Improved Single-Event Transient Hardness in Tunnel-Diode Body-Contact SOI nMOS

The physical mechanism of the time, emitter lateral dimension (AE) and low-high temperature dependent degradation under mixed-mode stress for C-doped SiGe HBTs (SiGe:C HBTs) on thin-film silicon-on-insulator (SOI) is investigated. We focus on the impact of mixed-mode stress on device characteristics such as base current (IB) and current gain (β) degradation rate, device scaling issue and low-high temperature.