Zhanglei Wang

Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns

At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too high; the 2005 International Roadmap for Semiconductors predicts that test-application times will be 30 times larger in 2010 than they are today. In addition, many new types of defects cannot be accurately modeled using existing fault models. Therefore, there is a need to model the quality of test patterns such that they can be quickly assessed for defect screening. Test selection is required to choose the most effective pattern sequences from large test sets. Current industry practice for test selection is based on fault grading, which is computationally expensive and must also be repeated for every fault model. Moreover, although efficient methods exist today, for fault-oriented test generation, there is a lack of understanding on how best to combine the test sets thus obtained, i.e., derive the most effective union of the individual test sets without simply taking all the patterns for each fault model. This paper presents the use of the output deviation as a surrogate coverage-metric for pattern modeling and test grading. A flexible, but general, probabilistic-fault model is used to generate a probability map for the circuit, which can subsequently be used for test-pattern reordering. The output deviations resulting from the probability map(s) are used as a coverage-metric to model test patterns; the higher the deviation, the better the quality of the test pattern. We show that, for the ISCAS benchmark circuits and as compared to other reordering methods, the proposed method provides ldquosteeperrdquo coverage curves for different fault models.

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling. An efficient linear feedback shift register (LFSR) reseeding technique is used as the compression engine. All cores on the SOC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits for the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that attempts to maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time (TAT) is minimized. This scheduling method is static in nature because it requires predetermined test cubes. We also present a dynamic scheduling method that performs test compression during test generation. Experimental results for International Symposium on Circuits and Systems and International Workshop on Logic and Synthesis benchmark circuits, as well as industrial circuits, show that optimum TAT, which is determined by the largest core, can often be achieved by the static method. If structural information is available for the cores, the dynamic method is more flexible, particularly since the performance of the static compression method depends on the nature of the predetermined test cubes.

Test Data Compression Using Selective Encoding of Scan Slices

We present a selective encoding method that reduces test data volume and test application time for scan testing of intellectual property (IP) cores. This method encodes the slices of test data that are fed to the scan chains in every clock cycle. To drive N scan chains, we use only c tester channels, where c=lceillog2(N+1)rceil+2 . In the best case, we can achieve compression by a factor of N/c using only one tester clock cycle per slice. We derive a sufficient condition on the distribution of care bits that allows us to achieve the best-case compression. We also derive a probabilistic lower bound on the compression for a given care-bit density. Unlike popular compression methods such as embedded deterministic test (EDT), the proposed approach is suitable for IP cores because it does not require structural information for fault simulation, dynamic compaction, or interleaved test generation. The on-chip decoder is small, independent of the circuit under test and the test set, and it can be shared between different circuits. We present compression results for a number of industrial circuits and compare our results to other recent compression methods targeted at IP cores.

Board-level fault diagnosis using Bayesian inference

Increasing integration densities and high operating speeds are leading to subtle manifestations of defects at the board level. Board-level functional test is therefore necessary for product qualification. The diagnosis of functional failures is especially challenging, and the cost associated with board-level diagnosis is escalating rapidly. An effective and cost-efficient board-level diagnosis strategy is needed to reduce manufacturing cost and time-to-market, as well as to improve product quality. In this paper, we use Bayesian inference to develop a new board-level diagnosis framework that allows us to identify faulty devices or faulty modules within a device on a failing board with high confidence. Bayesian inference offers a powerful probabilistic method for pattern analysis, classification, and decision making under uncertainty. We apply this inference technique by first generating a database of fault syndromes obtained using fault-insertion test at the module pin level on a fault-free board, and then use this database along with the observed erroneous behavior of a failing board to infer the most likely faulty device. Results on a case study using an open-source RISC system-on-chip highlight the effectiveness of the proposed framework in terms of fault-localization accuracy and correctness of diagnosis.

Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics

We propose a built-in self-test (BIST) procedure for nanofabrics implemented using chemically-assembled electronic nanotechnology. Several fault detection configurations are presented to target stuck-at faults, shorts, opens, and connection faults in nanoblocks and switchblocks. We also present an adaptive recovery procedure through which we can identify defect-free nanoblocks and switchblocks in the nanofabric-under-test. The proposed BIST, recovery, and defect tolerance procedures are based on the reconfiguration of the nanofabric to achieve complete fault coverage for different types of faults. We show that a large fraction of defect-free blocks can be recovered using a small number of BIST configurations. We also present simple bounds on the recovery that can be achieved for a given defect density. Simulation results are presented for various nanofabric sizes, different defect densities, and for random and clustered defects. The proposed BIST procedure is well suited for regular and dense architectures that have high defect densities

Deviation-Based LFSR Reseeding for Test-Data Compression

Linear feedback shift register (LFSR) reseeding forms the basis for many test-compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSR-reseeding-based compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects, particularly since there are often several candidate seeds for a test cube. We use the recently proposed output deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Experimental results are reported using test patterns for stuck-at and transition faults derived from selected seeds for the ISCAS-89 and the IWLS-05 benchmark circuits. These patterns achieve higher coverage for transition and stuck-open faults than patterns obtained using other seed-generation methods for LFSR reseeding. Given a pattern pair (p 1, p 2) for transition faults, we also examine the transition-fault coverage for launch on capture by using p 1 and p 2 to separately compute output deviations. Results show that p 1 tends to be better when there is a high proportion of do-not-care bits in the test cubes, while p 2 is a more appropriate choice when the transition-fault coverage is high.

Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks

Diagnosis of functional failures at the board level is critical for improving product yield and reducing manufacturing cost. State-of-the-art board-level diagnostic software is unable to cope with high complexity and ever-increasing clock frequencies, and the identification of the root cause of failure on a board is a major problem today. Ambiguous or incorrect repair suggestions lead to long debug times and even wrong repair actions, which significantly increases the repair cost and adversely impacts yield. We propose a smart diagnosis method based on artificial neural networks that can learn from repair history and accurately localize the root cause of a failure. Fine-grained fault syndromes extracted from failure logs and the corresponding repair actions are used to train the neural network. The proposed network structure is simple, it can be rapidly trained, and it is scalable to large datasets. Moreover, the relationship between typical syndromes and the most appropriate repair actions can be easily inferred from the network structure. An industrial board, which is currently in production, is used to validate the diagnosis approach in terms of diagnostic accuracy, resolution, and quantifiable improvement over current diagnostic software.

Diagnostic system based on support-vector machines for board-level functional diagnosis

Fault diagnosis is critical for improving product yield and reducing manufacturing cost. However, it is very challenging to identify the root cause of failures on a complex circuit board. Ambiguous diagnosis results lead to long debug times and even wrong repair actions, which significantly increases the repair cost. We propose an automatic diagnostic system using support vector machines (SVMs). The proposed system acquires debug knowledge from empirical data; this strategy avoids the difficulties involved in knowledge acquisition in traditional fault diagnosis methods. SVMs provide an optimal separating hyperplane in classification. The optimal solution and generalization ability of SVMs lead to higher diagnostic accuracy, compared to the classical learning approaches such as artificial neural networks (ANNs). An industrial board is used to validate the effectiveness of the proposed system. Extensive simulation results demonstrate that the SVMs-based diagnostic system provides quantifiable improvement over current diagnostic software and an ANN-based diagnostic system.

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don’t-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS’89 and ITC’99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression

LFSR reseeding forms the basis for many test compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSR-reseeding-based compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects. We use the recently proposed output deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Experimental results are reported using test patterns for stuck-at faults derived from selected seeds. These patterns achieve higher coverage for stuck-open and transition faults than patterns obtained using other methods.