Zhaobo Zhang

Board-Level Functional Fault Diagnosis Using Artificial Neural Networks, Support-Vector Machines, and Weighted-Majority Voting

Increasing integration densities and high operating speeds lead to subtle manifestation of defects at the board level. Functional fault diagnosis is, therefore, necessary for board-level product qualification. However, ambiguous diagnosis results lead to long debug times and even wrong repair actions, which significantly increase repair cost and adversely impact yield. Advanced machine-learning (ML) techniques offer an unprecedented opportunity to increase the accuracy of board-level functional diagnosis and reduce high-volume manufacturing cost through successful repair. We propose a smart diagnosis method based on two ML classification models, namely, artificial neural networks (ANNs) and support-vector machines (SVMs) that can learn from repair history and accurately localize the root cause of a failure. Fine-grained fault syndromes extracted from failure logs and corresponding repair actions are used to train the classification models. We also propose a decision machine based on weighted-majority voting, which combines the benefits of ANNs and SVMs. Three complex boards from the industry, currently in volume production, and additional synthetic data, are used to validate the proposed methods in terms of diagnostic accuracy, resolution, and quantifiable improvement over current diagnostic software.

Board-level fault diagnosis using Bayesian inference

Increasing integration densities and high operating speeds are leading to subtle manifestations of defects at the board level. Board-level functional test is therefore necessary for product qualification. The diagnosis of functional failures is especially challenging, and the cost associated with board-level diagnosis is escalating rapidly. An effective and cost-efficient board-level diagnosis strategy is needed to reduce manufacturing cost and time-to-market, as well as to improve product quality. In this paper, we use Bayesian inference to develop a new board-level diagnosis framework that allows us to identify faulty devices or faulty modules within a device on a failing board with high confidence. Bayesian inference offers a powerful probabilistic method for pattern analysis, classification, and decision making under uncertainty. We apply this inference technique by first generating a database of fault syndromes obtained using fault-insertion test at the module pin level on a fault-free board, and then use this database along with the observed erroneous behavior of a failing board to infer the most likely faulty device. Results on a case study using an open-source RISC system-on-chip highlight the effectiveness of the proposed framework in terms of fault-localization accuracy and correctness of diagnosis.

Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks

Diagnosis of functional failures at the board level is critical for improving product yield and reducing manufacturing cost. State-of-the-art board-level diagnostic software is unable to cope with high complexity and ever-increasing clock frequencies, and the identification of the root cause of failure on a board is a major problem today. Ambiguous or incorrect repair suggestions lead to long debug times and even wrong repair actions, which significantly increases the repair cost and adversely impacts yield. We propose a smart diagnosis method based on artificial neural networks that can learn from repair history and accurately localize the root cause of a failure. Fine-grained fault syndromes extracted from failure logs and the corresponding repair actions are used to train the neural network. The proposed network structure is simple, it can be rapidly trained, and it is scalable to large datasets. Moreover, the relationship between typical syndromes and the most appropriate repair actions can be easily inferred from the network structure. An industrial board, which is currently in production, is used to validate the diagnosis approach in terms of diagnostic accuracy, resolution, and quantifiable improvement over current diagnostic software.

Adaptive Board-Level Functional Fault Diagnosis Using Decision Trees

Functional fault diagnosis at board-level is desirable for high-volume production since it improves product yield. However, to ensure diagnosis accuracy and effective board repair, a large number of syndromes must be used. Therefore, the diagnosis cost can be prohibitively high due to the increase in diagnosis time and the complexity of syndrome collection/analysis. We propose an adaptive diagnosis method based on decision trees (DTs). Faulty components are classified according to the discriminative ability of the syndromes in DT training. The diagnosis procedure is constructed as a binary tree, with the most discriminative syndrome as the root and final repair suggestions are available as the leaf nodes of the tree. The syndrome to be collected in the next step is determined based on the observations of syndromes collected thus far in the diagnosis procedure. The number of syndromes required for diagnosis can also be significantly reduced compared to the number of syndromes used for system training. Diagnosis results for two complex boards from industry, currently in volume production, and additional synthetic data highlight the effectiveness of the proposed approach.

Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning

Advanced machine learning techniques offer an unprecedented opportunity to increase the accuracy of board-level functional fault diagnosis and reduce product cost through successful repair. Ambiguous or incorrect diagnosis results lead to long debug times and even wrong repair actions, which significantly increase repair cost. We propose a smart diagnosis method based on multikernel support vector machines (MK-SVMs) and incremental learning. The MK-SVM method leverages a linear combination of single kernels to achieve accurate faulty-component classification based on the errors observed. The MK-SVMs thus generated can also be updated based on incremental learning, which allows the diagnosis system to quickly adapt to new error observations and provide even more accurate fault diagnosis. Two complex boards from industry, currently in volume production, are used to validate the proposed diagnosis approach in terms of diagnosis accuracy (success rate) and quantifiable improvements over previously proposed machine-learning methods based on several single-kernel SVMs and artificial neural networks.

Diagnostic system based on support-vector machines for board-level functional diagnosis

Fault diagnosis is critical for improving product yield and reducing manufacturing cost. However, it is very challenging to identify the root cause of failures on a complex circuit board. Ambiguous diagnosis results lead to long debug times and even wrong repair actions, which significantly increases the repair cost. We propose an automatic diagnostic system using support vector machines (SVMs). The proposed system acquires debug knowledge from empirical data; this strategy avoids the difficulties involved in knowledge acquisition in traditional fault diagnosis methods. SVMs provide an optimal separating hyperplane in classification. The optimal solution and generalization ability of SVMs lead to higher diagnostic accuracy, compared to the classical learning approaches such as artificial neural networks (ANNs). An industrial board is used to validate the effectiveness of the proposed system. Extensive simulation results demonstrate that the SVMs-based diagnostic system provides quantifiable improvement over current diagnostic software and an ANN-based diagnostic system.

Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches

Multithreshold CMOS is very effective for reducing standby leakage power during long periods of inactivity. Recently, a power-gating scheme was presented to support multiple power-off modes and reduce the leakage power during short periods of inactivity. However, this scheme can suffer from high sensitivity to process variations, which impedes manufacturability. We propose a new power-gating technique that is tolerant to process variations and scalable to more than two intermediate power-off modes. The proposed design requires less design effort and offers greater power reduction and smaller area cost than the previous method. In addition, it can be combined with existing techniques to offer further static power reduction benefits. Analysis and extensive simulation results demonstrate the effectiveness of the proposed design.

Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector Machines

Advanced machine learning techniques offer an unprecedented opportunity to increase the accuracy of board-level functional fault diagnosis based on the historical data of successfully repaired boards. However, the training complexity increases significantly in diagnosis systems due to the increasing amount of the historical data. We propose a smart learning method in the diagnosis system using incremental support-vector machines (SVMs). The SVMs updated using incremental learning allow the diagnosis system to quickly adapt to new error observations and provide more accurate fault diagnosis. Two sets of large-scale synthetic data generated from the log information of two complex industrial boards, in volume production, are used to validate the proposed diagnosis approach in terms of training time and diagnosis accuracy over a previously proposed diagnosis system based on simple support-vector machines.

A Robust and Reconfigurable Multi-mode Power Gating Architecture

Multi-threshold CMOS is a very effective technique for reducing standby leakage power during long periods of inactivity. Recently, a power-gating scheme was presented to support multiple power-off modes and reduce the leakage power during short periods of inactivity. However, this scheme suffers from high sensitivity to process variations, which impedes manufacturability and also limits its applicability to at most two intermediate power-off modes. We propose a new power-gating technique that is tolerant to process variations and scalable to more than two intermediate power-off modes. In addition, the proposed design requires minimum design effort and offers greater power reduction and smaller area cost than the previous method. Analysis and extensive simulation results demonstrate the effectiveness of the proposed design.

Physical defect modeling for fault insertion in system reliability test

Hardware fault-insertion test (FIT) is a promising method for system reliability test and diagnosis coverage measurement. It improves the speed of releasing a quality diagnostic program before manufacturing and provides feedbacks of fault tolerance of a very complicated large system. Certain level insufficient fault tolerance can be fixed in the current system but others may require ASIC or overall system architectural modifications. The FIT is achieved by introducing an artificial fault (defect modeling) at the pin level of a module to mimic any physical defect behavior within the module, such as SEU (Single Event Upset) or escaped delay defect. We present a hardware architectural solution for pin fault insertion. We also present a simulation framework and optimization techniques for a subset of module pin selection for FIT, such that desired coverage are obtained under the constraints of limited FIT pins due to the costs of the associated implementation. Experimental results are presented for selected ISCAS and OpenCore benchmarks, as well as for an industrial circuit.