Zhangwen Tang

An 18-mW 1.175–2-GHz Frequency Synthesizer With Constant Bandwidth for DVB-T Tuners

A fully integrated 1.175-2-GHz differentially tuned frequency synthesizer aimed for digital video broadcasting-terrestrial tuners is implemented in a 0.18-mum CMOS process. To maintain phase-noise optimization and loop stability over the entire output frequency range, techniques of constant loop bandwidth are proposed. The voltage-controlled oscillator gain K VCO and band step f res are both maintained by simultaneously adjusting the sizes of switched capacitors and varactors. Charge pump current I CP is programmed to compensate the variation of the division ratio N . The measured results show an in-band phase noise of -97.6 dBc/Hz at a 10-kHz offset and an integrated phase error of 0.63 deg from 100 Hz to 10 MHz. The measured variations of K VCO and f res are less than 12.5% and 4.5%, respectively. The variations of the measured phase noise at 10-kHz and 1-MHz frequency offsets are less than 1 dB. The measured 3-dB closed-loop bandwidth is 110 kHz and the variation is less than 9%. The chip draws 10-mA current from a 1.8-V supply while occupying a 2.2-mm2 die area.

A 975-to-1960MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tuners

There is a high demand for high-performance tuners to meet the digital video broadcasting-terrestrial (DVB-T) standard. Often the DVB-T tuners employ a double-conversion zero-IF (DZIF) architecture that demands a wideband fractional-N synthesizer as the first local oscillator (LO1) to cover the frequency range of 975 to 1960MHz. This LO1 needs to meet a stringent phase-noise requirement with an adequate target phase noise of −87dBc/Hz at a 10kHz offset and integrated rms phase error less than 1° [1]. Because of the very wide frequency range, the variation of loop bandwidth may affect the phase-noise performance and loop stability.

A wideband CMOS variable gain low noise amplifier based on single-to-differential stage for TV tuner applications

A wideband CMOS variable gain low noise amplifier (VGLNA) used for TV tuner is presented. A single-to-differential (S2D) circuit other than an off-chip balun is applied for high gain mode and a resistive attenuator is for five steps (6 dB per step) attenuation in low gain mode. The performance of S2D, especially the noise factor is analyzed. The chip is implemented in a 0.18-mum 1P6M mixed-signal CMOS process. Measurements show that in the 50-860 MHz frequency range, the VGLNA achieves 15 dB maximum gain, 31 dB variable gain range, a minimum 3.8 dB noise figure and 2.6 dBm 11P3 at 15 dB gain while consumes 5.7 mA from a 1.8 V supply.

A CMOS wide-band low-noise amplifier with balun-based noise-canceling technique

A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only gamma/20 and the noise figure (NF) of the proposed LNA is 1 + 0.2gamma. The chip is implemented in a 0.18-mum MMRF CMOS process. Measured results show that in 50 M-860 MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply.

A 12 th order active-RC filter with automatic frequency tuning for DVB Tuner applications

A 12th order active-RC filter for DVB Tuner applications with automatic frequency tuning (AFT) is presented in this paper. The filter is implemented in Butterworth biquad structure. The AFT circuit is introduced to compensate the frequency variation by a 7-bits switched-capacitor array. The measurement results indicate that the precision of tuning circuit can be controlled less than plusmn2.3%, the in-band group delay variation is 70 ns, and the in-band IM3 achieves -60 dB with -27 dbm input power. This proposed filter circuit, fabricated in a SMIC 0.18 mum CMOS process, consumes 6 mA current with 1.8 V power supply.

A Low-phase-noise 1-GHz LC VCO Differentially Tuned by Switched Step Capacitors

This paper proposes a novel 1-GHz LC oscillator differentially tuned by switched step capacitors, which is implemented in a 0.25mum 1P5M CMOS process. A period calculation technique (PCT) is adopted to analyze the differential tuning characteristic of switched step capacitors. Due to the symmetric oscillation waveforms, the differentially tuned LC VCO has 7 dB phase noise reduction in the 1/f 3 region compared to the single-ended tuned topology, and 23.6dB CMRR. It achieves phase noise -83 dBc/Hz, -107 dBc/Hz and -130 dBc/Hz respectively at 10-kHz, 100-kHz and 1-MHz offsets, while dissipating 3.3 mA current at 2.6 V power supply. Chip size is 0.82 mm times 0.84 mm

A Wide-band CMOS Low-Noise Amplifier for TV Tuner Applications

In this paper, a wide-band CMOS low-noise amplifier (LNA) is presented, in which the thermal noise of the input MOSFET is canceled exploiting a noise-canceling technique. The LNA is designed under input/output impedance matching condition. And its noise figure (NF) and linearity analysis are investigated particularly. The LNA chip is implemented in a 0.25-mum 1P5M RF CMOS process. Measurement results show that in 50-860 MHz, the gain is about 13.4 dB, the NF is from 2.4 dB to 3.5 dB, and the input-referred third-order intercept point (IIP3) is 3.3 dBm. The chip consumes 30 mW at 2.5-V power supply and the core size is only 0.15 mm times 0.18 mm.

Standard CMOS technology on-chip inductors with pn junctions substrate isolation

New substrate isolation structures using pattern stacked pn junctions for on-chip inductors in standard CMOS technology are presented. For the first time, through increasing the reverse bias voltage to pn junctions, the lower substrate eddy loss due to the pn junction substrate isolation is reliably validated and the maximum quality factor is improved by 19%. The inductor without substrate shielding layer is compared to the inductor with metal one pattern ground shielding, pattern n-well, n/sup +/ diffusion, dual pn junctions isolation.

A 50-to-930MHz quadrature-output fractional-N frequency synthesizer with 770-to-1860MHz single-inductor LC-VCO and without noise folding effect for multistandard DTV tuners

There are many Digital TV (DTV) standards around the world, such as DVB-T/C/H in Europe, ATSC-C/M/H in North America, TDMB in China, ISDB-T in Japan and DMB-T in South Korea. In recent years, next generations of DVB standards (e.g. DVB-T2 and DVB-C2) are proposed, which adopt 256 QAM and even 4k QAM modulation to obtain higher performance. Often the DTV tuners employ a direct-conversion Zero-IF architecture, which demands the use of a wideband fractional-N synthesizer as the local oscillator (LO) to cover the frequency range of 50 to 900MHz. This LO needs to meet a very stringent phase noise requirement with an adequate target phase noise of -98dBc/Hz at a 10kHz offset and integrated rms phase error less than 0.25° [1]. However, it is well known that the performance of fractional-N PLLs is significantly influenced by the circuit nonlinearity. Nonlinearity results in the noise-folding phenomenon, which can seriously degrade the in-band phase noise and raise reference and fractional spurs [2].

An accurate 1.08-GHz CMOS LC voltage-controlled oscillator

An accurate 1.08-GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35/spl mu/m standard 2P4M CMOS process. In this paper we present a new convenient method of calculation of oscillating period. With this period calculation technique, the frequency tuning curves agree perfectly with the experiment. At a 3.3-V supply, the LC-VCO measures a phase noise of 82.2 dBc/Hz at a 10 kHz frequency offset while dissipating 3.1mA current. Chip size is 0.86mm /spl times/ 0.82mm.