Hao Min

A high-speed, programmable, CSD coefficient FIR filter

A new high-speed, programmable FIR filter is presented, which is a multiplierless filter with CSD encoding coefficients. We propose a new programmable CSD encoding structure to make CSD coefficients programmable. Compared with the conventional FIR structure with Booth multipliers, this coding structure improves the speed of filter and decreases the area. We design a 10-bits, 18-taps video luminance filter with the presented filter structure. The completed filter core occupies 6.8 /spl times/ 6.8 mm of silicon area in 0.6 /spl mu/m 2P2M CMOS technology, and its maximum work frequency is 100 MHz.

Robust Timing and Frequency Synchronization Scheme for DTMB System

In this paper a robust timing and frequency synchronization algorithm for DTMB system is developed. A two-step frequency offset estimation and compensation process is proposed to perform carrier recovery. Firstly coarse frequency estimation is achieved by utilizing the shift-and-add property of m-sequence. The second step finds the frame start position and the remaining frequency offset simultaneously. Meanwhile a timing tracking strategy is proposed to effectively track the dynamic changes in mobile environment. Thus the proposed scheme can resist large frequency offset and achieve accurate timing and frequency estimation. Simulation results under different channel situations verify the performance of the proposed scheme.

A Multi-Band Low-Noise Transmitter With Digital Carrier Leakage Suppression and Linearity Enhancement

A low-noise multi-band transmitter for GSM quad-band and WCDMA is presented. Programmable parameters of the analog baseband and the RF frontend enable adaption for different protocols and frequency bands. A three-step carrier leakage calibration algorithm is proposed to suppress the leakage to -65 dBm at highest RF gain. Novel linearization methods are used in the low-pass filter and the driver power amplifier to meet the demand of 3G systems. The noise floor achieves -157 dBc/Hz at 190 MHz frequency offset in WCDMA band, which eliminates the need for external SAW filter.

A fully differential charge pump with accurate current matching and rail-to-rail common-mode feedback circuit

A fully differential charge pump is proposed in this paper. It adopts the replica technique to eliminate the effect of channel-length modulation, and the charging and discharging currents can match well in a wide output range. A rail-to-rail common-mode feedback circuit is employed to ensure the large swing of the charge pump unrestricted. The charge pump is designed and fabricated in SMIC 0.18 mum CMOS process. The measured reference spur-level is about -73 dBc and the in-band phase noise is nearly -90 dBc/Hz@lKHz. The power dissipation of the charge pump is only 1 mW.

Hardware efficient decoding of LDPC codes using partial-min algorithms

In this paper, the partial-min algorithms are proposed for updating the check node messages in decoding low-density parity-check (LDPC) codes. The proposed methods can achieve a good performance-versus-complexity tradeoff by reducing both the check node processor complexity and the decoder memory requirements. Float-point and fixed-point simulation results show that a near optimum performance can be maintained. The architecture of a check node processor implementing the partial-min algorithms is also presented. The hardware expense especially the memory requirement is analyzed and compared with normal decoding architectures

A 3.2-to-4.6 GHz fast-settling all-digital PLL with feed forward frequency presetting

This paper presents a 3.2-to-4.6GHz fast-settling all digital fractional-N phase-locked loop (ADPLL) for multimode multiband receivers. Firstly, in this ADPLL, the wideband digitally controlled oscillator (DCO) is designed with a constant frequency step in the Coarse Mode to ensure constant loop bandwidth in the whole frequency range. Secondly, a feedforward presetting path between frequency command word (FCW) and oscillator tuning word in the Coarse Mode (OTWC) is utilized to accelerate the locking process for large frequency hopping steps. Thirdly, an adaptive locked and unlocked controller (ALUC) is used to allow frequency mode (Coarse/Medium/Fine Mode) to shift automatically. Implemented in a 65 nm CMOS process, the ADPLL on-chip part consumes 16mW at 1V voltage supply. The phase noise at 3.982GHz is −121.8 dBc/Hz@1MHz. The ADPLL with a final bandwidth of 65 kHz exhibits 55 μs transient settling time for a 1.232GHz frequency hopping.

A 24 GHz High Frequency-Sweep Linearity FMCW Signal Generator with Floating-Shield Distributed Metal Capacitor Bank

A 24 GHz FMCW generator based on ADPLL was implemented in this work. Two-point modulation technology was used to achieve high sweep linearity. Meanwhile, a floating shield distributed metal capacitor bank was proposed to provide high frequency-sweep linearity DCO. By using these technologies, the FMCW generators frequency error can be controlled as small as 60 kHzrms when 180 MHz frequency was swept in 1.3 ms. High speed part of the FMCW generator was fabricated in 65 nm CMOS technology and the low speed digital part was implemented on FPGA. Power consumption of the chip excluding IO buffers is 29 mW.

A triple-band flexible low-noise transmitter with linearity enhancement

A low-noise triple band transmitter for GSM triple-band and WCDMA is presented. By programming parameters, analog baseband and RF frontend can handle signals of different protocols and frequency bands. Novel linearization method is used in LPF and driver amplifier to meet the demand of 3G systems. Noise optimization is also adopted so that our transmitter achieves -157 dBc/Hz noise at 190 MHz frequency offset in WCDMA band, which eliminates external SAW filter.

Low-complexity synchronization technique with adaptive mode detection for DVB-H system

This paper presents a novel synchronization technique with adaptive mode detection feature for the DVB-H system. The proposed joint algorithm doesnt depend on the knowledge of the cyclic prefix length to accomplish the maximum likelihood correlation sum, compared with the conventional algorithm. A reliable adaptive mode detection scheme, including DFT points and cyclic prefix length detection, is also presented. It exploits the periodic character of the continuous correlation sum function as the decision criteria. In the frequency selective fading channel, this approach not only shortens the blind synchronization times but also reduces the implementation complexity by 91.3%

Prediction of LC-VCOs' tuning curves with period calculation technique

This paper describes a new prediction method of tuning curves of a LC-tank voltage-controlled oscillator (VCO) with period calculation technique. With this period calculation technique, the prediction of oscillator tuning curves is more accurate compared with the traditional harmonic approximation. The theoretical analyses are experimentally validated with a CMOS complementary LC-tank VCO implemented in 0.35/spl mu/m 1P4M pure logic CMOS process.