Zhao Fazhan

Impact of temperature on single event upset measurement by heavy ions in SRAM devices

The temperature dependence of single event upset (SEU) measurement both in commercial bulk and silicon on insulator (SOI) static random access memories (SRAMs) has been investigated by experiment in the Heavy Ion Research Facility in Lanzhou (HIRFL). For commercial bulk SRAM, the SEU cross section measured by 12C ions is very sensitive to the temperature. The temperature test of SEU in SOI SRAM was conducted by 209Bi and 12C ions, respectively, and the SEU cross sections display a remarkable growth with the elevated temperature for 12C ions but keep constant for 209Bi ions. The impact of temperature on SEU measurement was analyzed by Monte Carlo simulation. It is revealed that the SEU cross section is significantly affected by the temperature around the threshold linear energy transfer of SEU occurrence. As the SEU occurrence approaches saturation, the SEU cross section gradually exhibits less temperature dependency. Based on this result, the experimental data measured in HIRFL was analyzed, and then a reasonable method of predicting the on-orbit SEU rate was proposed.

Analysis and optimization of current sensing circuit for deep sub-micron SRAM

A quantitative yield analysis of a traditional current sensing circuit considering the random dopant fluctuation effect is presented. It investigates the impact of transistor size, falling time of control signal CS and threshold voltage of critical transistors on failure probability of current sensing circuit. On this basis, we present a final optimization to improve the reliability of current sense amplifier. Under 90 nm process, simulation shows that failure probability of current sensing circuit can be reduced by 80% after optimization compared with the normal situation and the delay time only increases marginally.

Study on the dose rate upset effect of partially depleted silicon-on-insulator static random access memory

This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM (Partially Depleted Silicon-On-Insulator Static Random Access Memory) with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM (Static Random Access Memory) chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. A specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about 1×108 Gy(Si)/s. However, there are a few bits upset when the dose rate reaches up to 1.58 × 109 Gy(Si)/s. The SRAM circuit can still work after the high level γ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations are made to improve the dose rate hardened performance of the PDSOI SRAM.