Luo Jiajun

The realization of an SVGA OLED-on-silicon microdisplay driving circuit

An 800 × 600 pixel organic light-emitting diode-on-silicon (OLEDoS) driving circuit is proposed. The pixel cell circuit utilizes a subthreshold-voltage-scaling structure which can modulate the pixel current between 170 pA and 11.4 nA. In order to keep the voltage of the column bus at a relatively high level, the sample-and-hold circuits adopt a ping-pong operation. The driving circuit is fabricated in a commercially available 0.35 μm two-poly four-metal 3.3 V mixed-signal CMOS process. The pixel cell area is 15 × 15 μm2 and the total chip occupies 15.5 × 12.3 mm2. Experimental results show that the chip can work properly at a frame frequency of 60 Hz and has a 64 grayscale (monochrome) display. The total power consumption of the chip is about 85 mW with a 3.3V supply voltage.

A new OLED SPICE model for pixel circuit simulation in OLED-on-silicon microdisplay design

A new equivalent circuit model of organic-light-emitting-diode (OLED) is proposed. As the single- diode model is able to approximate OLED behavior as well as the multiple-diode model, the new model will be built based on it. In order to make sure that the experimental and simulated data are in good agreement, the constant resistor is exchanged for an exponential resistor in the new model. Compared with the measured data and the results of the other two OLED SPICE models, the simulated I -V characteristics of the new model match the measured data much better. This new model can be directly incorporated into an SPICE circuit simulator and presents good accuracy over the whole operating voltage.

An improved driving circuit scheme applied in extreme low-current design on OLED-on-silicon microdisplay

This paper describes an improved driving circuit scheme including a slew-rate enhancement circuit for organic light-emitting-diode-on-silicon (OLEDoS) microdisplay design. Due to the basic pixel cell area of OLEDoS microdisplay being less than 300 μm2, pixel currents are always needed to modulate from hundreds of pico-amperes (pA) to tens of nano-amperes (nA). The proposed circuit can satisfy the timing requirements (the time period of video sample signal is about 30ns) at such low current. Extra circuits introduced by the improved driving circuit scheme have a simple structure and consume little additional power in static condition.

A new type of bootstrapped charge-recovery logic circuit

A new low power bootstrapped adiabatic logic circuit, Complement Pass-Transistor Bootstrapped Charge-Recovery Logic (CP-BCRL), is presented. CP-BCRL has more efficient energy transfer and recovery due to using the bootstrap technique and adiabatic logic. It consumes less energy and is insensitive to output load capacitance. The HSPICE simulation result is given which use the 0.6-um CMOS technology.

Estimation of pulsed laser-induced single event transient in a partially depleted silicon-on-insulator 0.18-μm MOSFET

In this paper, we investigate the single event transient (SET) occurring in partially depleted silicon-on-insulator (PDSOI) metal—oxide—semiconductor (MOS) devices irradiated by pulsed laser beams. Transient signal characteristics of a 0.18-μm single MOS device, such as SET pulse width, pulse maximum, and collected charge, are measured and analyzed at wafer level. We analyze in detail the influences of supply voltage and pulse energy on the SET characteristics of the device under test (DUT). The dependences of SET characteristics on drain-induced barrier lowering (DIBL) and the parasitic bipolar junction transistor (PBJT) are also discussed. These results provide a guide for radiation-hardened deep sub-micrometer PDSOI technology for space electronics applications.

Analysis and optimization of tunneling-FET based on SOI

In this paper, we optimized a heterojunction SOI-TFET with high-k dielectric overlap on SiGe-source region. Mole fraction (x) of the Si(x)Ge(1−x) has an important influence in the performance of the TFET. The optimized device has achieved 50.9mV/decades SS, which breaks the 60mV/decades SS barrier. It has realized 107 Ion/Ioff ratios and the OFF-state leakage current can be lowed to 10−14 A/µm level. The ON-state drain current can reach 10−6A/µm at VDS=0.3V and the device works well at VDS=0.2V. The proposed device is optimized using 2D Synopsys TCAD simulation.

DSOI—a novel structure enabling adjust circuit dynamically

A double silicon on insulator (DSOI) structure was introduced based on fully depleted SOI (FDSOI) technology. The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to N-channel and P-channel devices. Based on DSOI ring oscillator (OSC), this paper focused on the theoretical analysis and electrical test of how the OSCs frequency being influenced by the back gate electrodes (soi2n, soi2p). The testing results showed that the frequency and power consumption of OSC could change nearly linearly along with the back gate bias. According to the different requirements of the circuit designers, the circuit performance could be improved by positive soi2n and negative soi2p, and the power consumption could be reduced by negative soi2n and positive soi2p. The best compromise between performance and power consumption of the circuit could be achieved by appropriate back gate biasing.

Comparison of decoupling resistors and capacitors for increasing the single event upset resistance of SRAM cells

The effects of various values and combinations of decoupling resistors and capacitors on the single event upset (SEU) resistance of static random access memory (SRAM) cells with six transistors have been studied by Spice simulations based on a partially-depleted (PD) silicon-on-insulator (SOI) CMOS technology. It is found that there is an effect enhancement for the combination of the decoupling resistors and capacitors in increasing the SEU linear energy transfer (LET) threshold of the cell, compared with the sum of the SEU LET threshold increments resulting from the corresponding resistors and capacitors, respectively. Also, with the product of the resistance r and capacitance c being constant, a larger r produces a higher SEU LET threshold. In addition, the simulation results show that the LET threshold increases nonlinearly with r, while it does linearly with c.

Holding-voltage drift of a silicon-controlled rectifier with different film thicknesses in silicon-on-insulator technology

This paper presents a new phenomenon, where the holding-voltage of a silicon-controlled rectifier acts as an electrostatic-discharge protection drift in diverse film thicknesses in silicon-on-insulator (SOI) technology. The phenomenon was demonstrated through fabricated chips in 0.18 μm SOI technology. The drift of the holding voltage was then simulated, and its mechanism is discussed comprehensively through ISE TCAD simulations.