Zhao Yaqin

Automatic digital modulation recognition using artificial neural networks

This paper presents a modified structure and learning algorithm of artificial neural networks (ANN) for recognizing baseband signal modulation types in the presence of additive white Gaussian noise. The new method employs a layer with less output nodes and an error back propagation learning algorithm with momentum to improve the recognition performance. Simulation results and performance evaluation of the ANN are given and it is shown that the benefits of the developed method are that its structure is simple and it performs well at low signal to noise ratio (SNR) with high overall success rates.

Channelized receiver platform of SDR based on FPGAs

In this paper, a channelized receiver platform of software defined radio is developed which is mainly to realize wideband quadrature digitization, modulation classification and demodulation exploiting A/D converters. FPGAs with the combination of programmable DSPs. The front-end of researched receiver based on polyphase filter quadrature digitization processors, where digitization takes place at intermediate frequencies (IF), adopts a wideband design with a bandwidth of up to 100MHz and a centered carrier frequency of up to 250MHz. The low-complexity high-speed digital IF signal processing is carried out with CORDIC algorithm on FPGAs, then to realize the recognition of several modulation schemes such as 2ASK, 4ASK, 2PSK, 4PSK, 2FSK, 4FSK, 16QAM to implement communication protocols fairly flexibly.In this paper, a channelized receiver platform of software defined radio is developed which is mainly to realize wideband quadrature digitization, modulation classification and demodulation exploiting A/D converters. FPGAs with the combination of programmable DSPs. The front-end of researched receiver based on polyphase filter quadrature digitization processors, where digitization takes place at intermediate frequencies (IF), adopts a wideband design with a bandwidth of up to 100MHz and a centered carrier frequency of up to 250MHz. The low-complexity high-speed digital IF signal processing is carried out with CORDIC algorithm on FPGAs, then to realize the recognition of several modulation schemes such as 2ASK, 4ASK, 2PSK, 4PSK, 2FSK, 4FSK, 16QAM to implement communication protocols fairly flexibly.

A new approach of 2D discrete cosine transform with Mobius inverse formula

The 2D discrete cosine transform (DCT) is an important mathematical tool in digital image processing and many other fields. Our aim is mainly to present an algorithm of 2D DCT, which turns N/spl times/N DCT into N separate 1D DCT and addition operations, and then to implement DCT with an arithmetic Fourier transform (AFT), which has turned out to be an important alternative to the known traditional methods of fast Fourier transform (FFT) in terms of accuracy, complexity and speed. The total number of multiplications and additions is only half of that required for the corresponding traditional method. Simulation results show that this method is feasible and its computational complexity is lower than the row-column algorithm.

A study on implementing wavelet transform and FFT with FPGA

This paper shows how to implement the wavelet transform and the Fast Fourier Transform (FFT) with a Field Programmed Gate Array (FPGA). First, it introduces the implementation of the wavelet transform with lattice filters and achieves the FFT with the Coordinate Rotational Digital Computation (CORDIC). Then, the emulation data of the Daubechies D4 & D6 wavelet transforms and the FFT with 16 points are given, and their performances are analyzed. The results prove this to be a novel and effective method to implement the wavelet transform and the FFT with FPGA.