Zhenghao Lu

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-mum 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7plusmn0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets

Broad-Band Design Techniques for Transimpedance Amplifiers

In this paper, a novel bandwidth enhancement technique based on the combination of capacitive degeneration, broad-band matching network, and the regulated cascode (RGC) input stage is proposed and analyzed, which turns the transimpedance amplifier (TIA) design into a fifth-order low-pass filter with Butterworth response. This broad-band design methodology for TIAs is presented with an example implemented in CHRT 0.18-mum 1.8-V RF CMOS technology. Measurement data shows a -3-dB bandwidth of about 8 GHz with 0.25-pF photodiode capacitance. Comparing with the core RGC TIA without capacitive degeneration and broad-band matching network, this design achieves an overall bandwidth enhancement ratio of 3.6 with very small gain ripple. The transimpedance gain is 53 dBOmega with a group delay of 80plusmn20 ps. The chip consumes only 13.5-mW dc power and the measured average input-referred noise current spectral density is 18 pA/radicHz up to 10 GHz

Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback

In this paper, a novel current-mode transimpedance amplifier (TIA) exploiting the common gate input stage with common source active feedback has been realized in CHRT 0.18 ¿m -1.8 V RFCMOS technology. The proposed active feedback TIA input stage is able to achieve a low input impedance similar to that of the well-known regulated cascode (RGC) topology. The proposed TIA also employs series inductive peaking and capacitive degeneration techniques to enhance the bandwidth and the gain. The measured transimpedance gain is 54.6 dB¿ with a -3 dB bandwidth of about 7 GHz for a total input parasitic capacitance of 0.3 pF. The measured average input referred noise current spectral density is about 17.5 pA/¿{Hz} up to 7 GHz. The measured group delay is within 65 ± 10 ps over the bandwidth of interest. The chip consumes 18.6 mW DC power from a single 1.8 V supply. The mathematical analysis of the proposed TIA is presented together with a detailed noise analysis based on the van der Ziel MOSFET noise model. The effect of the induced gate noise in a broadband TIA is included.

Design of probabilistic-based Markov Random Field logic gates in 65nm CMOS technology

As the VLSI technology node is getting into the sub-100nm regime, the reliability issues caused by random interferences such as noise, process variations and manufacturing defects are changing the nature of digital computation from deterministic to probabilistic. This paper studies the principle of probabilistic-based Markov Random Field (MRF) design methodology for CMOS static logic gates. The MRF design technique is able to significantly improve the reliability and interference tolerance of the logic circuits. A Differential Cascode Voltage Switch (DCVS) based MRF logic design method is proposed, which presents substantial noise immunity improvement over the normal MRF logic circuits. The proposed method is validated by simulation in 65nm CMOS technology.

A novel low complexity soft-decision demapper for QPSK 8PSK demodulation of DVB-S2 systems

This paper provides an efficient low complexity soft-decision demapper algorithm for computing the log-likelihood-ratios (LLRs) of the 8PSK demodulations in the DVB-S2 standard. The proposed method has linear complexity, avoids the multiple square operations in the classical method and reduces the number of compare-select operations by half compared to traditional LLR computation algorithms. The demapper using the proposed method has been verified on Altera FPGA.

Bandwidth-Related Optimization in High-Speed Frequency Dividers using SiGe Technology

In this paper, the trade-off related to bandwidth of high-speed common-mode logic frequency divider is analyzed in detail. A method to optimize the operating frequency, band-width as well as power consumption is proposed. This method is based on bipolar device characteristics, whereby a negative resistance model can be used to estimate the optimal normalized upper frequency and lower frequency of frequency dividers under different conditions, which is conventionally ignored in literatures. This method provides a simple but efficient procedure in designing high performance frequency dividers for different applications. To verify the proposed method, a static divide-by-2 at millimeter wave ranges is implemented in 180 nm SiGe technology. Measurement results of the divider demonstrate significant improvement in the figure of merit as compared with literatures.

Leakage reduction of sub-55nm SRAM based on a feedback monitor scheme for standby voltage scaling

Reducing standby supply voltage to DRV can sharply decrease leakage power. In this paper, a feedback monitor scheme for standby VDD scaling is proposed. The feedback scheme utilizes the same memory cell to obtain exactly the same performance with SRAM core cells and thus to monitor approximate DRV tail of SRAM array. Based on Monte-Carlo DRV distribution along with its dependencies on body-bias and source-bias voltage, we add controlling options to regulate the DRV of monitor cells and then to approach the worst-case DRV of core cells. The feedback monitor scheme for detecting DRV is implemented with bank-based SRAM design. Simulation results on 55nm CMOS process indicates that for a 512KB SRAM, leakage power savings are achieved in different process corners compared to conventional SRAM structure.

A 60GHz BiCMOS self-demodulator with injection locked oscillator

This paper proposes a wide-band self-demodulating receiver for 60GHz ISM band applications. The proposed receiver architecture self-demodulates the OOK input signal by using injection locked oscillator and passive mixer. This simple architecture features extremely ultra-lower-power consumption and faster settling time. Implemented in Tower Jazz 180nm SiGe technology with 200GHz fT, the proposed receiver is able to work at the 60GHz ISM-band frequency range with an OOK data rate up to 2Gbps. The current consumption of the whole receiver is less than 15mA from a single 1.8V supply.

A 100MHz — 2GHz wireless receiver in 40-nm CMOS for software-defined radio

Software-defined radio (SDR), one of solutions to realize multi-mode terminal for mobile communication standards, has attracted intensive studies. A wideband wireless receiver is designed in a 40-nm CMOS process for SDR, which can cover the frequency range from 100MHz to 2GHz. The wideband RF front-end includes a low noise amplifier (LNA), a mixer, intermediate frequency amplifier (IF AMP) and a variable gain amplifier (VGA). The focal point of the design lies in the wideband LNA. The wideband inductorless LNA with 1.1-V supply is a two-stage amplifier that can operates from 100MHz to 2GHz. The noise figure (NF) of the LNA is 2.2–2.4 dB while it can achieve gains of 24-12 dB and 0– •12 dB when working under the active mode and passive mode, respectively. The whole system provides a NF of 3.2–3.5 dB with 5.02mw power consumption.

A 1.2-GHz bandwidth variable gain amplifier with continuous dB-linear control in 65nm CMOS

In this paper, a wideband variable gain amplifier (VGA) is designed in 65nm CMOS technology. The proposed VGA is composed of two cascading variable gain cells. Each gain cell employs a simple single-stage pseudo-exponential topology to realize continuous decibel in linear gain control and low power consumption. Two cascading cells realize a VGA with more than 50dB decibel in linear gain tuning range and 1.2-GHz-3dB bandwidth. The proposed wideband VGA consumes about 1.2mA current from a single 1.2V supply and is suitable for analog baseband signal processing in 60-GHz wireless communication systems. Furthermore, the proposed design is realized only based on CMOS devices without inductor and resistor which means small area and insensitive to process variation.