Boyu Hu

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection

A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm2 in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4

A Capacitor-DAC-Based Technique For Pre-Emphasis-Enabled Multilevel Transmitters

\mu \text{W}

Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers

/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.

An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design

This brief presents a capacitor digital-to-analog converter (DAC) based technique that is suitable for pre-emphasis-enabled multilevel wireline transmitter design in voltage mode. Detailed comparisons between the proposed technique and conventional direct-coupling-based as well as resistor-DAC-based multilevel transmitter design techniques are given, revealing potential benefits in terms of speed, linearity, implementation complexity, and also power consumption. A PAM-4 transmitter with 2-Tap feed-forward equalization adopting the proposed technique is implemented in 65-nm CMOS technology. It achieves a 25-Gb/s data rate and energy efficiency of 2 mW/Gb/s.

DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers

A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from -88 to -109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from -16.8 to -34.6dBc, when operating at 2.4GHz.

An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search

This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed in terms of its speed, power consumption, and linearity. A voltage-mode PAM-4 transmitter with 2-tap FFE utilizing the proposed architecture is implemented in the 65-nm CMOS technology. It achieves a data rate of 34 Gb/s and an energy efficiency of 2.7 mW/Gb/s.

An 8.8-GS/s 8b Time-Interleaved SAR ADC with 50-dB SFDR Using Complementary Dual-Loop-Assisted Buffers in 28nm CMOS

In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. It demonstrates a phase noise reduction from −88 to −109 dBc/Hz at 1-MHz offset and an integrated phase noise reduction from −16.8 to −34.6 dBc when operating at 2.4 GHz.

A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications

This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.