Zhenglin Liu

An Energy-Efficient AES-CCM Implementation for IEEE802.15.4 Wireless Sensor Networks

As the networking technology greatly advanced in past decades, Wireless Sensor Networks (WSN) have been widely deployed and utilized in various areas. Security issues on WSN devices thus draw much attention. In order to ensure the security of IEEE802.15.4 WSN and to fulfill the strict limitations of area and energy, we propose an efficient scheme for AES-CCM architecture. We implement AES-CCM by taking into account the tradeoff among throughput, area and power consumption. Our design employs a full-hardware implementation to offload CPU. Meanwhile, we parallelize CTR and CBC-MAC processing to cut down duty cycles and energy-consumption. An appropriate 8-bit data path AES architecture is chosen to guarantee rigorous requirements of the area and energy. Furthermore, a shared key expansion is applied to reduce the die-size. Experimental results based on the United Microelectronics Corporation (UMC) 0.25 micrometers 1.8 volts technology library show that our implementation is compact and energy-efficient, which would be suitable for resource-constrained WSN devices.

A trustworthy key generation prototype based on DDR3 PUF for wireless sensor networks.

In wireless sensor security systems, the security key of sensor node is usually stored in the non-volatile memory. By capturing the nodes, it is possible for attackers to perform a physical invasive attack to extract the key illegally. Physical unclonable function (PUF) has its innate immunity to physical invasive attacks, which can effectively generate keys from manufacturing variability of a device. The feasibility of DRAM PUF based on DDR3 memory is studied in the paper though theory analysis and experiments. A prototype of key extraction based on DRAM PUF is proposed. As DRAM is widely used as memory device in WSN nodes, the generation of DRAM PUF keys need no extra hardware, which making it applicable for compact WSN circuits.

Design of highly efficient elliptic curve crypto-processor with two multiplications over GF(2163)

Abstract In this article, a parallel hardware processor is presented to compute elliptic curve scalar multiplication in polynomial basis representation. The processor is applicable to the operations of scalar multiplication by using a modular arithmetic logic unit (MALU). The MALU consists of two multiplications, one addition, and one squaring. The two multiplications and the addition or squaring can be computed in parallel. The whole computations of scalar multiplication over GF(2163) can be performed in 3 064 cycles. The simulation results based on Xilinx Virtex2 XC2V6000 FPGAs show that the proposed design can compute random GF(2163) elliptic curve scalar multiplication operations in 31.17 μs, and the resource occupies 3 994 registers and 15 527 LUTs, which indicates that the crypto-processor is suitable for high-performance application.

Multiloop Minimum Switching Cycle Control Based on Nonaveraged Current Discrete-Time Model for Buck Converter

Exploring high-performance controller for buck converter is challenging since it can be easily affected by converter model accuracy. In this paper, a novel nonaveraged current discrete-time (NCD) model is proposed, in which inductor current is expressed as time-varying equations during switch-on and switch-off states. It achieves higher accuracy than the conventional averaged model at high-frequency range, thus can be used to optimize high-speed controller design. Based on the NCD model, a multiloop minimum switching cycle (MMSC) control strategy, composed of output feedback (OF), line feed forward (LFF), and reference feed forward (RFF) loops, is proposed and tuned for buck converter operating in continuous conduction mode. Mutual influences among three loops are considered and eliminated by specifically designed LFF and RFF compensations, which adapt the OF compensation. With consideration of sampling and calculation delays, relationship between transient switching cycles and geometric center of controller poles is discovered from a calculated output voltage error series. Furthermore, theoretical minimum switching cycles are calculated by moving the center inside the unit cycle of complex plane, which ensures system stability. Moreover, load/line transient response and reference tracking time are simultaneously optimized to the minimum switching cycles. Effectiveness of the controller is proved by converter closed-loop pole/zero plots, transient response simulations, and experiments.

PUFKEY: a high-security and high-throughput hardware true random number generator for sensor networks.

Random number generators (RNG) play an important role in many sensor network systems and applications, such as those requiring secure and robust communications. In this paper, we develop a high-security and high-throughput hardware true random number generator, called PUFKEY, which consists of two kinds of physical unclonable function (PUF) elements. Combined with a conditioning algorithm, true random seeds are extracted from the noise on the start-up pattern of SRAM memories. These true random seeds contain full entropy. Then, the true random seeds are used as the input for a non-deterministic hardware RNG to generate a stream of true random bits with a throughput as high as 803 Mbps. The experimental results show that the bitstream generated by the proposed PUFKEY can pass all standard national institute of standards and technology (NIST) randomness tests and is resilient to a wide range of security attacks.

A Trustworthy Key Generation Prototype Based on DDR3 PUF for Wireless Sensor Networks

In wireless sensor security systems, the security key of sensor node is usually stored in the non-volatile memory. By capturing the nodes, it is possible for attackers to perform a physical invasive attack to extract the key illegally. Physical unclonable function (PUF) has its innate immunity to physical invasive attacks, which can effectively generate keys from manufacturing variability of a device. The feasibility of DRAM PUF based on DDR3 memory is studied in the paper though theory analysis and experiments. A prototype of key extraction based on DRAM PUF is proposed. As DRAM is widely used as memory device in WSN nodes, the generation of DRAM PUF keys need no extra hardware, which making it applicable for compact WSN circuits.

Off-Chip Memory Encryption and Integrity Protection Based on AES-GCM in Embedded Systems

To ensure the overall security of embedded systems with off-chip memories, it is essential to safeguard the confidentiality and integrity of the data that travels between the system-on-chip part of the embedded system and the off-chip memory. This article presents a novel low-overhead architecture to achieve this goal.

An Anti-Electromagnetic Attack PUF Based on a Configurable Ring Oscillator for Wireless Sensor Networks

Wireless sensor networks (WSNs) are an emerging technology employed in some crucial applications. However, limited resources and physical exposure to attackers make security a challenging issue for a WSN. Ring oscillator-based physical unclonable function (RO PUF) is a potential option to protect the security of sensor nodes because it is able to generate random responses efficiently for a key extraction mechanism, which prevents the non-volatile memory from storing secret keys. In order to deploy RO PUF in a WSN, hardware efficiency, randomness, uniqueness, and reliability should be taken into account. Besides, the resistance to electromagnetic (EM) analysis attack is important to guarantee the security of RO PUF itself. In this paper, we propose a novel architecture of configurable RO PUF based on exclusive-or (XOR) gates. First, it dramatically increases the hardware efficiency compared with other types of RO PUFs. Second, it mitigates the vulnerability to EM analysis attack by placing the adjacent RO arrays in accordance with the cosine wave and sine wave so that the frequency of each RO cannot be detected. We implement our proposal in XINLINX A-7 field programmable gate arrays (FPGAs) and conduct a set of experiments to evaluate the quality of the responses. The results show that responses pass the National Institute of Standards and Technology (NIST) statistical test and have good uniqueness and reliability under different environments. Therefore, the proposed configurable RO PUF is suitable to establish a key extraction mechanism in a WSN.

PEM: a lightweight program memory encryption mechanism for embedded processor

Abstract Application of embedded systems is faced with multiple threats against security. To solve this problem, this article proposes a new program memory encryption mechanism (PEM) to enhance the security of embedded processor. The new mechanism encrypts all the programs via a secure cache structure. It not only caches the instructions read from the off-chip memory, but also stores the pad values used to encrypt the plaintext. It effectively accelerates encryption and reduces the performance overhead. Besides the encryption, PEM also monitors the program modifications and reset behaviors to reduce the risk of vicious tamper. The experiment indicates that PEM has an average of 2.3 % performance improvement and results in a 25.71 % power reduction in the write-back stage. The new scheme offers a good balance between performance and security. It is fully practicable for embedded processor.

Pitfall of the Strongest Cells in Static Random Access Memory Physical Unclonable Functions

Static Random Access Memory (SRAM) Physical Unclonable Functions (PUFs) are some of the most popular PUFs that provide a highly-secured solution for secret key storage. Given that PUF responses are noisy, the key reconstruction must use error correcting code (ECC) to reduce the noise. Repetition code is widely used in resource constrained systems as it is concise and lightweight, however, research has shown that repetition codes can lead to information leakage. In this paper we found that the strongest cell distribution in a SRAM array may leak information of the responses of SRAM PUF when the repetition code is directly applied. Experimentally, on an ASIC platform with the HHGRACE 0.13 μm process, we recovered 8.3% of the measured response using the strongest cells revealed by the helper data, and we finally obtained a clone response 79% similar to weak response using the public helper data. We therefore propose Error Resistant Fuzzy Extractor (ERFE), a 4-bit error tolerant fuzzy extractor, that extracts the value of the sum of the responses as a unique key and reduces the failure rate to 1.8 × 10−8 with 256 bit entropy.