Xuecheng Zou

Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric.

Abstract Thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet or dry N 2 anneal. The effects of Ti content on the performance of HfTiO gate dielectric are investigated by using different sputtering powers for the Ti target. Experimental results indicate that as the Ti content increases, the dielectric constant ( κ ) can increase up to 40 for a Ti content of 28%. However, when the Ti content is too high, the interface properties and gate leakage properties are deteriorated. On the contrary, results show that owing to the hydrolyzable property of GeO x , the wet-N 2 anneal can greatly suppress the growth of unstable low- κ GeO x interlayer, resulting in lower interface-state density and gate leakage current, in addition to larger κ value. In this study, when the sputtering power of the Ti target is 80xa0W together with a 25-W power for the Hf target and a post-deposition anneal (PDA) in wet-N 2 ambient at 500xa0°C for 300xa0s, excellent device performance is achieved: equivalent oxide thickness of 0.72xa0nm, equivalent dielectric constant of 39, interface-state density of 6.5xa0×xa010 11 xa0eV −1 xa0cm −2 and gate leakage current of 5.7xa0×xa010 −4 xa0A/cm 2 at V g xa0=xa01xa0V. Therefore, in order to obtain high-quality HfTiO gate dielectric for small-scaled Ge MOS devices, not only should the Ti content be optimized, the PDA should also be done in a wet-N 2 ambient.

New analysis and design of a RF rectifier for RFID and implantable devices.

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from −15 dBm to −4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitableto passive UHF RFID tag IC and implantable devices.

Suppressed growth of unstable low-k GeOx interlayer in Ge metal-oxide-semiconductor capacitor with high-k gate dielectric by annealing in water vapor

The effects of water vapor added in the N2 annealing of high-k HfTiON gate dielectric on Ge metal-oxide-semiconductor capacitor are investigated. Both transmission-electron microscopy and ellipsometry indicate that, as compared to dry-N2 annealing, the wet-N2 annealing can greatly suppress the growth of unstable low-k GeOx at the dielectric/Ge interface, thus resulting in smaller equivalent dielectric thickness, as well as less interface states and dielectric charges. All these are attributed to the hydrolyzable property of GeOx in water. Moreover, the wet-N2 annealed capacitor has ten times lower gate-leakage current due to its better dielectric morphology as confirmed by atomic force microscopy.

Design and Implementation of An ECC-Based Digital Baseband Controller for RFID Tag Chip

The extremely constrained resource has hindered the efforts to implement the elliptic curve cryptography (ECC) into a radio-frequency identification (RFID) tag chip. In this paper, an ECC-based RFID digital baseband controller (DBC), which is compatible with ISO/IEC 14443 and Schnorr authentication protocol, is presented. In order to achieve low resources consumption and fast ECC computation speed, some techniques, such as the register reuse, clock multiplexer, and asynchronous counter, are adopted in this design. In addition, a linear feedback shift register-based stream encryption scenario is proposed for the data security. According to the synthesis result, the gate area and power consumption of DBC are 25.7 K and 14.7 μW, respectively, in UMC 0.13 μm CMOS technology. All of those characteristics make the realization of ECC-based DBC for RFID tag chip promising.

An Efficient and Flexible Hardware Implementation of the Dual-Field Elliptic Curve Cryptographic Processor

Elliptic curve cryptography (ECC) has been widely used for the digital signature to ensure the security in communication. It is important for the ECC processor to support a variety of ECC standards to be compatible with different security applications. Thus, a flexible processor which can support different standards and algorithms is desired. In this paper, an efficient and flexible dual-field ECC processor using the hardware–software approach is presented. The proposed processor can support arbitrary elliptic curve. An elaborate modular arithmetic logic unit is designed. It can perform basic modular arithmetic operations and achieve high efficiency. Based on our designed instruction set, the processor can be programmed to perform various point operations based on different algorithms. To demonstrate the flexibility of our processor, a point multiplication algorithm with power analysis resistance is adopted. Our design is implemented in the field-programmable gate array platform and also in the application-specified integrated circuit. After implemented in the 55xa0nm CMOS process, the processor takes between 0.60xa0ms (163xa0bits ECC) and 6.75xa0ms (571xa0bits ECC) to finish one-point multiplication. Compared to other related works, the merits of our ECC processor are the high hardware efficiency and flexibility.

Digital Sensorless Current Mode Control Based on Charge Balance Principle and Dual Current Error Compensation for DC–DC Converters in DCM

For discontinuous conduction mode (DCM) dc–dc converters with digital sensorless current mode (DSCM) control, an observed current error occurs, owing to a low-accuracy current observer. Moreover, a reference current error occurs due to a low-accuracy current controller or a finite dc gain of current loop. Conventionally, the observed current is compensated to increase current regulation accuracy, whereas the reference current error is neglected. However, for charge balance principle (CBP)-based DSCM (CBP-DSCM) control, this paper proves that the reference current should be compensated in a same quantity to that of observed current. Otherwise, single or unequal compensation leads to output voltage steady-state error. For this reason, a dual current error compensation strategy for CBP-DSCM control is proposed. It compensates the errors in a same quantity through a current error observer, which considers parasitics and calculates the current errors without approximation. To verify the proposed strategy, small-signal models with parasitics for both the converter and the controller are constructed by differential functions of key variables. Furthermore, converter stability is analyzed at typical operation condition, while the stability at various operation conditions is verified through robustness analysis. Finally, simulations and experimental results verify the analysis and the improved transient response of the converter.

Design and Implementation of a RF Powering Circuit for RFID Tags or Other Batteryless Embedded Devices

A RF powering circuit used in radio-frequency identification (RFID) tags and other batteryless embedded devices is presented in this paper. The RF powering circuit harvests energy from electromagnetic waves and converts the RF energy to a stable voltage source. Analysis of a NMOS gate-cross connected bridge rectifier is conducted to demonstrate relationship between device sizes and power conversion efficiency (PCE) of the rectifier. A rectifier with 38.54% PCE under normal working conditions is designed. Moreover, a stable voltage regulator with a temperature and voltage optimizing strategy including adoption of a combination resistor is developed, which is able to accommodate a large input range of 4 V to 12 V and be immune to temperature variations. Latch-up prevention and noise isolation methods in layout design are also presented. Designed with the HJTC 0.25 μm process, this regulator achieves 0.04 mV/°C temperature rejection ratio (TRR) and 2.5 mV/V voltage rejection ratio (VRR). The RF powering circuit is also fabricated in the HJTC 0.25 μm process. The area of the RF powering circuit is 0.23 × 0.24 mm2. The RF powering circuit is successfully integrated with ISO/IEC 15693-compatible and ISO/IEC 14443-compatible RFID tag chips.

Threshold Voltage Model of SiGe Channel pMOSFET without Si Cap Layer

An analytical model on the threshold voltage of SiGe-channel pMOSFET without Si cap layer is developed by solving the Poissons equation. Energy-band offset induced by SiGe strained layer, short-channel effect and drain-induced barrier lowering effect are taken into account in the model. To evaluate the validity of the model, simulated results are compared with experimental data and results from BSIM4, and good agreements are confirmed.

A Low-Cost Low-Power Ring Oscillator-Based Truly Random Number Generator for Encryption on Smart Cards

The design of a low-cost low-power ring oscillator-based truly random number generator (TRNG) macrocell, which is suitable to be integrated in smart cards, is presented. The oscillator sampling technique is exploited, and a tetrahedral oscillator with large jitter has been employed to realize the TRNG. Techniques to improve the statistical quality of the ring oscillatorbased TRNGs bit sequences have been presented and verified by simulation and measurement. A postdigital processor is added to further enhance the randomness of the output bits. Fabricated in the HHNEC 0.13-μm standard CMOS process, the proposed TRNG has an area as low as 0.005 mm2. Powered by a single 1.8-V supply voltage, the TRNG has a power consumption of 40 μW. The bit rate of the TRNG after postprocessing is 100 kb/s. The proposed TRNG has been made into an IP and successfully applied in an SD card for encryption application. The proposed TRNG has passed the National Institute of Standards and Technology tests and Diehard tests.

A Sensorless Predictive Current Controlled Boost Converter by Using an EKF with Load Variation Effect Elimination Function

To realize accurate current control for a boost converter, a precise measurement of the inductor current is required to achieve high resolution current regulating. Current sensors are widely used to measure the inductor current. However, the current sensors and their processing circuits significantly contribute extra hardware cost, delay and noise to the system. They can also harm the system reliability. Therefore, current sensorless control techniques can bring cost effective and reliable solutions for various boost converter applications. According to the derived accurate model, which contains a number of parasitics, the boost converter is a nonlinear system. An Extended Kalman Filter (EKF) is proposed for inductor current estimation and output voltage filtering. With this approach, the system can have the same advantages as sensored current control mode. To implement EKF, the load value is necessary. However, the load may vary from time to time. This can lead to errors of current estimation and filtered output voltage. To solve this issue, a load variation elimination effect elimination (LVEE) module is added. In addition, a predictive average current controller is used to regulate the current. Compared with conventional voltage controlled system, the transient response is greatly improved since it only takes two switching cycles for the current to reach its reference. Finally, experimental results are presented to verify the stable operation and output tracking capability for large-signal transients of the proposed algorithm.