Zhezhi He

RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device

This paper presents a new Reconfigurable dualmode In-Memory Processing Architecture based on spin Hall effect-driven domain wall motion device called RIMPA. In this architecture, a portion of spintronic memory array can be reconfigured to either non-volatile memory or in-memory logic. Accordingly, computation can be performed within memory without long distance data transfer or large in-memory logic area overhead concerning conventional Von-Neumann or in-memory computing architecture, respectively. The device to architecture simulation results show that, with 17% area increase, RIMPA improves the operating energy by 72.2% as compared with the conventional non-volatile in-memory logic schemes. We show that the Advanced Encryption Standard (AES) algorithm which is widely used in secure big data storage, can be efficiently mapped to RIMPA with 68.8% and 20.8% energy saving in comparison to CMOS-ASIC and recent DW-AES implementations, respectively.

Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices

In this paper, we propose an energy efficient in-memory computing platform based on novel 4-terminal spin Hall effect-driven domain wall motion devices that could be employed as both non-volatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to architecture level simulation results show that, with 45% area increase, the proposed in-memory computing platform achieves the write energy 15.6 ~ fJ/bit which is more than one order lower than that of standard 1-transistor 1-magnetic tunnel junction counterpart while keeping the identical 1ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3% as compared with the conventional nonvolatile in-memory logic designs.

A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator

Current-mode Analog-to-Digital Converter (ADC) has drawn many attentions due to its high operating speed, power and ground noise immunity, and etc. However, 2n -- 1 comparators are required in traditional n-bit current-mode ADC design, leading to inevitable high power consumption and large chip area. In this work, we propose a low power and compact current mode Multi-Threshold Comparator (MTC) based on giant Spin Hall Effect (SHE). The two threshold currents of the proposed SHE-MTC are 200μA and 250μA with 1ns switching time, respectively. The proposed current-mode hybrid spin-CMOS flash ADC based on SHE-MTC reduces the number of comparators almost by half (2n-1), thus correspondingly reducing the required current mirror branches, total power consumption and chip area. Moreover, due to the non-volatility of SHE-MTC, the front-end analog circuits can be switched off when it is not required to further increase power efficiency. The device dynamics of SHE-MTC is simulated using a numerical device model based on Landau-Lifshitz-Gilbert (LLG) equation with Spin-Transfer Torque (STT) term and SHE term. The device-circuit co-simulation in SPICE (45nm CMOS technology) have shown that the average power dissipation of proposed ADC is 1.9mW, operating at 500MS/s with 1.2 V power supply. The INL and DNL are in the range of 0.23LSB and 0.32LSB, respectively.

Composite spintronic accuracy-configurable adder for low power Digital Signal Processing

Approximate Computing as a promising approach in Digital Signal Processing applications has been extensively analyzed to trade off limited accuracy loss for improvements in other circuit metrics, such as area, power, and speed. Most previous works on approximate circuit design have hardwired the degree of approximation in their implementations. This significantly limits their applicability, since inherent resilience varies significantly within applications. To address this limitation, in this paper, we propose a compact and energy efficient accuracy-configurable adder design based on a composite spintronic device structure consisting of magnetic domain wall motion stripe and magnetic tunnel junction. By leveraging the intrinsic current-mode thresholding operation of the spintronic device, we initially propose a hybrid Spin-CMOS majority gate and then we employ it to design an accuracy-configurable full adder cell. The proposed adder is equipped with a control knob to regulate energy-efficiency and the output quality trade-offs by modulating the circuit into two distinct operation modes (approximation and precision) to obtain acceptable output quality and reduced power consumption. The device-circuit SPICE simulations show 34.58% and 66% improvement in power consumption for precision and approximation modes, respectively, over recently reported Domain Wall Motion-based full adder design. The area-efficient accuracy-configurable adder also exhibits 19% improvement in circuit complexity over state-of-the-art CMOS FA design. We demonstrate the efficacy of our proposed adder in discrete cosine transform computation for a digital image processing architecture.

Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption

The logic-in-memory architecture is highly promising for high-throughput data-driven applications. This paper presents a novel dual-mode magnetic crossbar architecture consisting of perpendicularly cross-coupled magnetic racetrack nanowires, which could morph between non-volatile multi-bit racetrack memory mode and in-memory data encryption mode. The proposed magnetic crossbar is able to automatically perform parallel in-memory bit-wise XOR computations of the data stored in the racetrack memories with the help of magnetic coupling physics without complex peripheral circuits, which could be leveraged to design energy efficient in-memory data encryption engine. We employ Advanced Encryption Standard (AES) algorithm to elucidate the efficiency of the proposed design. The device-to-architecture level simulation results show that the proposed architecture can achieve 70% and 17.5% lower energy consumption compared to CMOS-ASIC and recent domain wall (DW) AES implementations, respectively. In addition, the AES encryption speed increases by 29.7% compared to the DW-AES implementation.

Current-Induced Dynamics of Multiple Skyrmions With Domain-Wall Pair and Skyrmion-Based Majority Gate Design

As an intriguing, ultrasmall, particle-like magnetic texture, skyrmions have attracted a lot of research interest for next-generation, ultradense, low-power magnetic memory/logic designs. Previous studies have demonstrated a single skyrmion domain-wall pair collision in a specially designed magnetic racetrack junction. We investigate the dynamics of multiple skyrmions with a domain-wall pair in a magnetic racetrack. The numerical micromagnetic simulation results indicate that the domain-wall pair could be pinned or depinned by a rectangular notch pinning site depending on both the number of skyrmions in the racetrack and the magnitude of driving current density. Such an emergent dynamical property could be used to implement a threshold-tunable step function in which the inputs are skyrmions and the threshold may be tuned by the driving current density. Threshold-tunable step functions are widely used in logic and neural network applications. We also present a three-input skyrmion-based majority logic gate design to demonstrate the potential application of such dynamic interactions of multiple skyrmions and domain-wall pairs.

Low power in-memory computing based on dual-mode SOT-MRAM

In this paper, we propose a novel Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array design that could simultaneously work as non-volatile memory and implement a reconfigurable in-memory logic (AND, OR) without add-on logic circuits to memory chip as in traditional logic-in-memory designs. The computed logic output could be simply read out like a normal MRAM bit-cell using the shared memory peripheral circuits. Such intrinsic in-memory logic could be used to process data within memory to greatly reduce power-hungry and long distance data communication in conventional Von-Neumann computing systems. We further employ in-memory data encryption using Advanced Encryption Standard (AES) algorithm as a case study to demonstrate the efficiency of the proposed design. The device to architecture co-simulation results show that the proposed design can achieve 70.15% and 80.87% lower energy consumption compared to CMOS-ASIC and CMOL-AES implementations, respectively. It offers almost similar energy consumption as recent DW-AES implementation, but with 60.65% less area overhead.

In-Memory Computing with Spintronic Devices

In-Memory computing has drawn many attentions as a promising solution to reduce massive power hungry data traffic between computing and memory units, leading to significant improvement of entire system performance and energy efficiency. Emerging spintronic device based non-volatile memory is becoming a next-generation universal memory candidate due to its non-volatility, zero leakage power in un-accessed bit-cell, high integration density, excellent endurance and compatibility with CMOS fabrication technology. In this paper, we present that different spintronic devices based memory, including spin-orbit torque magnetic random access memory (SOT-MRAM), domain wall motion memory, magnetic racetrack memory, could be leveraged to implement logic functions within memory without add-on logic circuits. As a case study, we employ Advanced Encryption Standard (AES) algorithm to elucidate the efficiency of such in-memory computing based on spintronic memory.

High performance and energy-efficient in-memory computing architecture based on SOT-MRAM

In this paper, we propose a novel Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array design that could either work as non-volatile memory or implement a reconfigurable in-memory logic (AND/OR/XOR) without addon logic circuits to memory chip as in conventional logic-in-memory designs. The computed logic output could be simply read out like a typical MRAM bit-cell through the modified memory peripheral circuits. Such intrinsic in-memory logic could be used to process data locally to greatly reduce power-hungry and long distance data communication in conventional Von Neumann computing systems. In this work, we further employ in-memory data encryption using Advanced Encryption Standard (AES) algorithm as a case study to demonstrate the efficiency of the proposed design. The device to architecture co-simulation results show that the proposed in-memory data encryption design can achieve 71.2% and 17.3% lower energy consumption compared to CMOS-ASIC and recent Domain Wall (DW)-AES implementations, respectively. Furthermore, it shows ∼ 33% reduction in area compared to DW-AES.

A tunable magnetic skyrmion neuron cluster for energy efficient artificial neural network

Artificial neuron is one of the fundamental computing unit in brain-inspired artificial neural network. The standard CMOS based artificial neuron designs to implement non-Unear neuron activation function typically consist of large number of transistors, which inevitably causes large area and power consumption. There is a need for novel nanoelectronic device that can intrinsically and efficiently implement such complex non-Unear neuron activation function. Magnetic skyrmions are topologically stable chiral spin textures due to Dzyaloshinskii-Moriya interaction in bulk magnets or magnetic thin films. They are promising next-generation information carrier owing to ultra-small size (sub-10nm), high speed (>100n]/s) with ultra-low depinning current density (MA/cm2) and high defect tolerance compared to conventional magnetic domain wall motion devices. In this work, to the best of our knowledge, we are the first to propose a threshold-tunable artificial neuron based on magnetic skyrmion. Meanwhile, we propose a Skyrmion Neuron Cluster (SNC) to approximate non-linear soft-limiting neuron activation functions, such as the most popular sigmoid function. The device to system simulation indicates that our proposed SNC leads to 98.74% recognition accuracy in deep learning Convolutional Neural Network (CNN) with MNIST handwritten digits dataset Moreover, the energy consumption of our proposed SNC is only 3.1 fj/step, which is more than two orders lower than that of CMOS counterpart.