Shaahin Angizi

Designing efficient QCA logical circuits with power dissipation analysis

Recently reported QCA logical and arithmetic designs have completely disregarded the power consumption issue of the circuits. In this paper, a comprehensive power dissipation analysis as well as a structural analysis over the previously published five-input majority gates is performed. During our experimentations, we found that these designs suffer from high power consumption and also structural weaknesses. Therefore, a new ultra-low power and low-complexity five-input majority gate is proposed. For examining our presented design in large array of QCA structures even parity generators, as instances of logical circuits with different lengths up to 32 bits are presented. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from implementation requirements and power consumption aspects. QCADesigner tool is used to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool.

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata

Quantum-dot cellular automata is one of the candidate technologies used in Nano scale computer design and a promising replacement for conventional CMOS circuits in the near future. Since memory is one of the significant components of any digital system, designing a high speed and well-optimized QCA random access memory (RAM) is a remarkable subject. In this paper, a new robust five-input majority gate is first presented, which is appropriate for implementation of simple and efficient QCA circuits in single layer. By employing this structure, a novel RAM cell architecture with set and reset ability is proposed. This architecture has a simple and robust structure that helps achieving minimal area, as well as reduction in hardware requirements and clocking zone numbers. Functional correctness of the presented structures is proved by using QCADesigner tool. Simulation results confirm efficiency and usefulness of the proposed architectures vis-i?-vis state-of-the-art. We propose a new robust QCA structure for five-input majority gate.The proposed gate is efficient for implementation of QCA circuits in a single layer.By integrating the proposed gate into a Memory cell, a controllable RAM cell is gained.

Designing quantum-dot cellular automata counters with energy consumption analysis

Quantum-dot cellular automata (QCA) exhibits a new paradigm at nanoscale for possible substitution of conventional CMOS technology. Most of the research works in QCA domain have completely ignored the significance of energy consumption constraint in designing circuits. In this study a low complexity and energy-efficient QCA T flip-flip as well as high-performance single-layer synchronous counters are proposed. By cascading the proposed T flip-flop and a suitable level converter, a QCA-compatible structure for falling edge triggered T flip-flop is achieved. This circuit functions as the chief element for constructing synchronous counters. QCADesigner and QCAPro tools are used for evaluating the functionality and calculating dissipated energy of the circuits, respectively. Results indicate the superiority of the proposed circuits in terms of complexity, latency and energy consumption as compared to their state-of-the-art counterparts. The proposed T flip-flop demonstrates 18% leakage energy improvement besides the considerable value of 56% switching energy improvement in 0.5Ek tunneling energy level as compared to the best ones. It is worth mentioning that 41%, 44% and 45% optimizations in the number of cells in addition to 15%, 25% and 33% optimizations in the area are achieved for the proposed mod 4, mod 8 and mod 16 counters, respectively, in comparison with the best previous results.

Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells

Abstract Quantum-dot cellular automata is one of the most prominent nanotechnologies considered to continue scaling-down trend of sub-micron electronics. Therefore, numerous combinational and sequential circuits have been redesigned and implemented using this new technology. Considering QCA full adder cell as the basic building block in designing arithmetic circuits, great deals of attention have been paid to this research field targeting to diminish circuit latency and complexity. In this paper, contrary to conventional gate-level implementation approaches used in QCA technology, a new explicit interaction approach is utilized for designing QCA circuits. Thus, in the first step, a new well-optimized structure for three-input Exclusive-OR gate (TIEO) is proposed that is based on cell interaction. Accordingly, a low complexity and ultra-high speed QCA one-bit full-adder cell is designed employing this structure. In the next step, a comprehensive energy consumption analysis and comparison is performed over previously published QCA full-adder cells and the proposed design. QCADesigner and QCAPro tools are used for verifying circuit functioning and estimating dissipated energy.

Efficient QCA Exclusive-or and Multiplexer Circuits Based on a Nanoelectronic-Compatible Designing Approach

Quantum-dot cellular automata (QCA) are a transistorless computation approach which encodes binary information via configuration of charges among quantum dots. The fundamental QCA logic primitives are majority and inverter gates which can be utilized to design various QCA circuits. This study presents a novel approach to designing efficient QCA-based circuits based on Boolean expressions achieved from reconfiguration of five-input and three-input majority gates. Whereas the multiplexer and Exclusive-or are the most important fundamental logical circuits in digital systems, designing efficient and single layer structures without coplanar cross-over wiring is advantageous in QCA technology. In order to demonstrate the efficiency and usefulness of the proposed approach, simple and dense multiplexer and Exclusive-or structures are implemented. The proposed designs have significant improvement in terms of area, complexity, latency, and gate count in comparison to previous designs. The correct logical functionalities of presented structures have been authenticated using QCA designer tool.

Towards ultra-efficient QCA reversible circuits

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption, and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most cost-efficient designs presented so far, with a reduction of 24%. In order to employ the merits of reversibility, the proposed reversible gate is leveraged to design the four common latches (D latch, T latch, JK latch, and SR latch). Specialized structures of the proposed circuits could be used as building blocks in designing sequential and combinational circuits in QCA architectures.

Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops

Quantum-dot Cellular Automata (QCA) is an attractive nanoelectronics paradigm which is widely advocated as a possible replacement of conventional CMOS technology. Designing memory cells is a very i...

Quantum-dot cellular automata circuits with reduced external fixed inputs

Abstract Nanotechnologies, notably quantum-dot cellular automata, have achieved world-wide attentions for their prominent features as compared to the conventional CMOS circuitry. Quantum-dot cellular automata, particularly owning to its considerable reduction in size, energy consumption and latency of circuits, is considered as a potential alternative for the CMOS technology. Considering the manufacturing aspects, in this paper, a method is proposed for designing efficient quantum-dot cellular automata circuits. We inspect an alternative approach for streamlined design of quantum-dot cellular automata circuits such that the required external fixed inputs are substantially reduced. In order to demonstrate the efficiency of the proposed method, the widely used multiplexer, XOR and party generator circuits are considered as case studies. All of the proposed circuits are simulated and verified using QCADesigner which is a valid and popular simulation tool. Comparisons indicate that the proposed method considerably reduces the number of external fixed inputs which simplifies the overall circuit implementation and fabrication.

RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device

This paper presents a new Reconfigurable dualmode In-Memory Processing Architecture based on spin Hall effect-driven domain wall motion device called RIMPA. In this architecture, a portion of spintronic memory array can be reconfigured to either non-volatile memory or in-memory logic. Accordingly, computation can be performed within memory without long distance data transfer or large in-memory logic area overhead concerning conventional Von-Neumann or in-memory computing architecture, respectively. The device to architecture simulation results show that, with 17% area increase, RIMPA improves the operating energy by 72.2% as compared with the conventional non-volatile in-memory logic schemes. We show that the Advanced Encryption Standard (AES) algorithm which is widely used in secure big data storage, can be efficiently mapped to RIMPA with 68.8% and 20.8% energy saving in comparison to CMOS-ASIC and recent DW-AES implementations, respectively.

Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices

In this paper, we propose an energy efficient in-memory computing platform based on novel 4-terminal spin Hall effect-driven domain wall motion devices that could be employed as both non-volatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to architecture level simulation results show that, with 45% area increase, the proposed in-memory computing platform achieves the write energy 15.6 ~ fJ/bit which is more than one order lower than that of standard 1-transistor 1-magnetic tunnel junction counterpart while keeping the identical 1ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3% as compared with the conventional nonvolatile in-memory logic designs.