Zhiheng Huang

Effect of solder bump geometry on the microstructure of Sn–3.5 wt% Ag on electroless nickel immersion gold during solder dipping

Continuous miniaturization of solder joints in high-density packaging makes it important to study how the joint size could affect the solder microstructure and thereby the subsequent in-service reliability. In this study, a printed circuit board with electroless nickel immersion gold (i.e., Au/Ni–P) over Cu bond pads of size approximately ∼80 μm and ∼1500 μm in diameter was dipped into a Sn–3.5Ag solder bath. The study shows that the smaller bumps, which cool more quickly, include much finer Ag 3 Sn particles. In addition, substantial differences in the thickness of the interfacial intermetallics and the microstructure for different dipping times are observed for different bump sizes. The results from a combined thermodynamic–kinetic model also suggest that the solder bump geometry can influence the dissolution kinetics of the pad metal into the molten solder and therefore the microstructure at the solder-pad interface and within the bulk solder.

Effects of the microstructure of copper through-silicon vias on their thermally induced linear elastic mechanical behavior

Through-silicon vias (TSVs) have been investigated extensively in recent years. However, the physical mechanisms behind some of the common problems associated with TSVs, such as the protrusion of Cu vias, are still unknown. In addition, since the dimensions of TSVs have been shrunk to microscopic levels, the sizes of the microstructural features of TSVs are no longer small compared to the dimensions of the vias. Therefore, the role and importance of the microstructural features of TSVs need to be studied to enable more accurate reliability predictions. This study focused on the effects the microstructural features of TSVs, i.e., the Cu grains and their [111] texture, grain size distribution, and morphology, have on the thermally induced linear elastic behavior of the vias. The results of the study indicate that stress distribution in the model that takes into account the Cu grains, whose Young’s moduli and Poisson’s ratios are set according to their crystallographic orientations, is more heterogeneous than that in a reference model in which the bulk properties of Cu are used. Stresses as high as 250 MPa are observed in the via of the model that takes into consideration the Cu grains, while stresses in the via of the reference model are all lower than 150 MPa. In addition, smaller Cu grains in the vias result in higher stresses; however, the variation in stress owning to changes in the grain size is within 20 MPa. The frequency of the stresses ranging from 80 MPa to 100 MPa was the highest in the stress distribution of the vias, depending on boundary conditions. The stress level in the v ias decreases with the decrease in the number of grains with the [111] texture. Finally, the stress level is lower in the model in which the grain structure is generated using a phase field model and is closer to that of the microstructures present in real materials.

A Method for Quantification of the Effects of Size and Geometry on the Microstructure of Miniature Interconnects

Because the heterogeneity of microstructure has significant effects on the material properties of ultrafine interconnects, it should be quantified, to facilitate high-fidelity prediction of reliability. To address this challenge, a method based on autocorrelation and singular value decomposition is proposed for quantitative characterization of microstructure. The method was validated by developing a quantitative relationship between reported microstructure and tensile strength for SnAgCuRE solders reported in the literature. The method was used to study the effects of size and geometry in ultrafine Sn37Pb interconnects on microstructure and von Mises stress, which were obtained simultaneously by coupling a phase-field model with an elastic mechanical model. By use of this method the degree of heterogeneity of the microstructure in relation to preferred growth directions of the phases was quantified by use of a scalar microstructure index. It was found that microstructure heterogeneity increases with decreasing standoff height, and is higher for hourglass-shaped solder joints. The average von Mises stress was found to be positively related to the microstructure index. The strong correlation between microstructure index and average von Mises stress was confirmed by nonlinear regression analysis using an artificial neural network. This indicates that the mechanical behavior of ultrafine interconnects can be predicted more accurately on the basis of the microstructure index.

The influences of grain size distributions on thermal-stresses in Cu-TSV

The dimensions of copper through-silicon vias (Cu-TSVs) have been shrunk to a microscopic scale, where the sizes of the copper grains are comparable to the vias, and thus the microstructure of the copper in the vias should be taken into consideration for reliability predictions. This paper focuses on the influences of the grain size distributions on the thermal-mechanical behaviors of the TSVs. Copper grains in TSVs are generated by both the Voronoi algorithm and a phase field method. The equations relating the yield stress and the Youngs modulus with respect to grain size are derived from experimental data. Two different boundary conditions are applied to the TSV models in the thermal-mechanical simulations and the thermal stresses of the microstructural models are calculated using the finite element method (FEM). The results from the microstructural models are then compared with the results from the reference model which ignores the grain structures. The results show that the copper grains can influence the thermal stresses in the via with negligible effects on other regions of the TSV. Smaller grains result in higher stresses, and the increase in stress can be as high as 30 MPa. The influence of the grain size distribution on thermal stress depends on the location of the grains as well as the applied boundary conditions. The grains with similar sizes in different grain structures can exhibit a difference in thermal stress around 10 MPa, whereas a difference in the boundary condition can lead to a completely different stress distribution.

Modeling the interdependence of processing and alloy composition on the evolution of microstructure in Sn-based lead-free solders in fine pitch flip chip

Market demands and legislation are driving the electronics-manufacturing sector to move rapidly toward a lead-free future, with Pb-containing electronics products to be banned in Europe after 2006. Although the related scientific research has been undertaken for a decade, a number of technical complications still exist, which are further exacerbated due to the concurrent developments in miniaturization and multifunctionality of microelectronic products. As the packaging joint geometry shrinks toward a microscopic scale, the joint fabrication and reliability become extremely sensitive to the composition and resulting microstructure generated from the chosen joining process and materials. The current level of understanding of such issues is still in its infancy and therefore requires further fundamental study. Thermodynamic modeling is employed in this work as a computational tool to study the sensitivity of processing ranges (e.g., reflow temperature) and the resultant reliability of the microjoints by changing the alloying elements and their content in Sn-based lead-free systems. The work is implemented using the MTDATA program developed by the National Physical Laboratory. With a newly developed database containing critically assessed thermodynamic data appropriate for lead-free solder systems, MTDATA allows the prediction of the liquid-solid transformation and phase formation, for example, as a function of chemical composition and temperature. The paper emphasizes the formation and mass fraction of intermetallic precipitates of different phases in the bulk solder joints and the modeling is also validated through experimental work and recent literature. The results are expected to assist the optimization of processing parameters and cost-effective production using lead-free solders.

An atomistic study of copper extrusion in through-silicon-via using phase field crystal models

Three-dimensional system integration using Cu through-silicon-via (TSV) technology enables vertical interconnection of stacked dies. However, the large statistical distribution of plastic Cu extrusion, also known as Cu pumping, presents a serious reliability concern. Traditional finite element method (FEM) based thermo-mechanical modeling that neglects microstructure has been extensively attempted in order to identify the root cause of the extrusion, which yet remains unknown. This study utilizes recently developed phase field crystal (PFC) models, which resolve systems on atomic length scales and diffusive timescales, to capture the creation, destruction, and interaction of defects in polycrystalline Cu TSV structures and thereby elucidate the atomistic mechanisms of the Cu extrusion. The governing kinetic equation of the PFC model is first solved using FEM to generate Cu grains with an atomic resolution in TSVs by referring to experimental EBSD images. A shearing term is then added to the governing equation to simulate TSV deformation under shear strain. The solidification process at the atomistic scale is simulated to prepare polycrystalline TSV samples. Rotation and coalescence of grains with low mis-orientations are observed in solidification. The application of shear strain to the polycrystalline TSVs reveals the movement of defects at the atomistic scale. The defects diffuse through grain boundaries and aggregate at the edges of TSVs, where the defects become immobile. The process of rotation and coalescence of grains is found to be accelerated under the shear strain. The simulation results also suggest that the geometry of the TSVs is an important factor controlling the behavior of defect diffusion and microstructures in TSVs, and thus the mechanical behavior of TSVs.

The geometrical effects in a model coupled with microstructural evolution and mechanical behavior for small-scale solder joints

The effects of stress, size, geometry, and composition on the microstructure in small-scale Sn-Pb solder joints are investigated by using a model coupled with microstructural evolution and mechanical behavior. The growth of both the Pb-rich phase and the Sn-rich phase along the boundaries of the solder joints is observed under an external shear stress and boundary constraints on diffusion. This result indicates that the microstructure in small-scaled solder joints is sensitive to stress. In addition, the heterogeneity of microstructure tends to increase with the shrinking of solder joint size. In particular, the size of the Sn-rich phase is observed to be nearly 1/5 of the standoff height in the solder joint with 1.5 μm pad size. The size effect on the microstructural heterogeneity is more pronounced in the hourglass-shaped joints than in the barrel-shaped counterparts. Furthermore, a larger volume fraction of the well-connected Sn-rich phase is found in the solder joints of a higher content of Sn. The heterogeneous microstructures exert influences on the stress distribution in the joints because the stress concentrates in the Sn-rich phase. The correlation between stress and microstructure is stronger in the hourglass geometry.

Effect of microstructure on thermal-mechanical stress in 3D copper TSV structures

Electronic packaging technologies have developed into the 3D packaging era and the TSV structure is one of the possible technological routes. TSVs of small scales such as submicron or even nano scales are envisioned for 3D packaging. From a material point of view, microstructure and its related micro-processes involved at such small scales will have important impacts on the performance of the electronic packages. This paper focuses on modeling the microstructural effects on the thermal-mechanical behavior of Cu-TSVs. In the microstructural models, Cu grains inside the vias are simulated using the Voronoi algorithm. The Youngs moduli and Poissons ratios of different grains are determined by their crystallographic orientations. A coupled thermal-mechanical finite element analysis is then carried out to study the microstructural effects. The temperature distribution is not significantly affected by the non-uniform thermal conductivities in this study. The stress distribution in the anistropic model exhibits considerable differences from that of the reference model in which the vias are treated as bulk materials. The stress within the vias varies significantly and there are sites where the stress is as high as 240 MPa, which has not been found in the reference model. Therefore, the effects of microstructures inside the Cu TSV are obvious and the microstructures should be among the design factors for reliable 3D electronic packaging.

On reproducing the copper extrusion of through-silicon-vias from the atomic scale

Three-dimensional system integration with through-silicon-vias (TSVs) is regarded as a promising solution to the “More-than-Moore” challenge to improve the performance of micro- and nano-electronic devices. However, the copper extrusion of TSVs during the back-end-of-the-line (BEOL) process and under service conditions poses serious reliability concerns. Substantial experimental and simulation work have been carried out to clarify the origins of copper extrusion, which as yet remain unclear. This study uses a two-mode phase field crystal (PFC) model to reproduce the process of the copper extrusion from the atomic scale. A “penalty term” is added to the governing equations of the PFC model to simulate the application of a compressive strain to the TSV samples. The application of strain reveals the process of emission and annihilation, and the climb and slip motions of dislocations. In general, the irreversible plastic extrusion is a cumulative effect of the motion of dislocations and the migration of the grain boundaries. The simulation results also suggest that the applied strain rate and the grain structure of the polycrystalline TSVs are important factors controlling the process of copper extrusion.

Materials and Processing of TSV

This chapter introduces the critical steps involved in fabricating through-silicon vias (TSVs) and associated materials. The fabrication steps for TSVs begin with etching of high aspect ratio trenches in Si, followed by placement of dielectric, barrier and seed layers, TSV filling and polishing, and then assembly with other components of a device. In addition, planarization, die-thinning and flow processes to fabricate TSV-enabled 3-D architectured microelectronic package are described. Challenges associated with processing of TSVs as well as methods for overcoming them are highlighted and discussed.