Zhijia Yang

A CMOS hysteresis undervoltage lockout with current source inverter structure

This paper describes a simple architecture and low power consumption undervoltage lockout (UVLO) circuit with hysteretic threshold. The UVLO circuit monitors the supply voltage and determines whether or not the supply voltage satisfies a predetermined condition. The under voltage lockout circuit is designed based on CSMC 0.5um CMOS technology, utilizing a relatively few amount of circuitry. It is realized with a current source inverter. The threshold voltage is determined by the W/L ratio of current source inverter and resistor in reference generator. The hysteresis is realized by using a feedback circuit to overcome the bad disturbance and noise rejection of the single threshold. Hysteretic threshold range is 40mV. The quiescent current is about 1uA at 3V supply voltage,while the power of circuit consumes only 3uW.

Traffic Aware Multiple Slotframes scheduling algorithm in industrial IoT applications using IEEE802.15.4e TSCH

In order to solve the problem of scheduling delay-constrain heterogeneous data traffic in wireless industrial network, we propose the Traffic Aware Multiple Slotframes scheduling algorithm. It includes two main procedures: Compute available slot set and Allocate communication resources according to the requirement of data traffic. And then we give the detail description of the algorithm used in star topology and tree topology. We adopt the theoretically well-established graph theory methods of matching and coloring to solve the problem of communication resources allocation in tree topology. The experimental results show that the proposed method can achieve highly reliability and energy efficiency over other strategies that follows the new trend of developing green networking and support the emerging IoT application.

A GFSK transceiver for IEEE Std. 802.15.4g used in China

This paper details on the design of GFSK (Gaussian frequency shift keying) transceiver with low-complexity high-performance low power consumption, which is compliant with IEEE Std. 802.15.4g used in China. In this architecture of transceiver, the capability of suppression phase noises is improved by employing fractional-N divider synthesizer with the 3rd-order sigma delta modulator, and the power consumption is also saved for using a discrete-time quadricorrelator with simple stucture in demodulator. Meanwile, system simulation results show, corresponding to other transceivers, this architecture is optimized and presents a good tolerance for carrier frequency offset within ± 50KHz.

Analysis on some key features of motion control network

Network technology promotes motion-control system to develop with high speed, high accuracy and high efficiency. Motion-control application also promotes motion-control network higher requires on communication rate, network-scheduling, clock-synchronization, communication- reliability, and so on. Based on studying architecture of motion-control network, this article emphasizes on network-scheduling strategy and clock-synchronization method.

Low complexity synchronization algorithms for HART C8PSK

This paper not only describes novel fast synchronization algorithms for HART C8PSK carrier recovery and symbol timing, but also provides a solution for HART C8PSK low power design. Synchronization is divided into two parts: initialization and tracking, the former part of which uses novel algorithms to attain equilibrium state quickly, and the later part of which is time-divided carried out. On basis of the proposed algorithms, high power component—equalizer and interpolator, can work at lowest rate, which indirectly reduces the system power. The implementation of those algorithms needs no additional hardware resource except a few lookup tables, and at the same time, they add negligible power consumption to the whole system. Simulations showed that the proposed synchronization algorithms can work very well in low SNR.

Research of design and verification of fieldbus communication control ASIC FBC100-H1

This paper proposes a new system structure of FBC100-H1 (foundation FieldBus communication control ASIC) and introduces its theory and implementation method. By using VMM verification methodology, the authors build up the verification environment of FBC100-H1 and enable it to obtain 100% function coverage. FBC100-H1 has taped out successfully and reached its every expected target.