Zhijin Hu

A Compact Bi-Direction Scannable a-Si:H TFT Gate Driver

An integrated a-Si:H thin-film transistors (TFTs) gate driver on array with both forward and backward scanning function is proposed. The single stage of the gate driver only consists of seven TFTs. The bi-direction scannable function is just realized by controlling the turning-on sequence of two input TFTs. Both scanning modes use the same driving TFT for pulling-up and pulling-down the output voltage and the same circuit unit for holding the low level. The proposed gate driver is fabricated in the 4.5 G TFT production line, and the measurements with the fabricated drivers verify the feasibility of the proposed driver.

Integrated a-Si:H Gate Driver With Low-Level Holding TFTs Biased Under Bipolar Pulses

A hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver on array with low-level holding TFTs (LLH TFTs) biased under bipolar pulse is investigated. It is shown that the bipolar bias at low frequency significantly alleviates the threshold voltage shift of the LLH TFTs. As a result, the lifetime of the proposed gate driver is demonstrated to be several times of that under the conventional unipolar pulse bias. In addition, the improvement in the lifetime becomes more significant at the higher work temperature. The liquid crystal display television panels (32-in, 1366 × RGB × 768) with the proposed a-Si:H gate drivers integrated on array are manufactured, and the feasibility of the proposed driving scheme is well verified.

Threshold Voltage Shift Effect of a-Si:H TFTs Under Bipolar Pulse Bias

Threshold voltage shift (ΔVTH) effect of hydrogenated amorphous silicon thin-film transistors under bipolar pulse bias stress (BPBS) is investigated. The dependence of the ΔVTH effect on the signal pulsewidth, stress temperature, and negative pulse voltage magnitude of the BPBS is systematically measured, and explained by the charge trapping and detrapping theory. Results show that the BPBS leads to a noticeably suppressed ΔVTH, compared with the conventional unipolar pulse bias stress. It is suggested that the BPBS with proper negative pulse voltage magnitude and low pulse frequency is an effective way of suppressing ΔVTH, especially when the thin-film transistors work relatively at high temperature.

One Gate Diode-Connected Dual-Gate a-IGZO TFT Driven Pixel Circuit for Active Matrix Organic Light-Emitting Diode Displays

A dual-gate (DG) amorphous indium-gallium- zinc-oxide thin-film transistor (TFT)-driven pixel circuit for active-matrix organic light-emitting diode displays is presented. One gate of the DGs serves as a primary gate (PG) and the other as an auxiliary gate (AG). The threshold voltage (V_TH) of the DG TFT under the PG operation is modulated by the AG bias voltage. The VTH variation (ΔV_TH) is compensated with the AG and the drain diode-connected structure. The validity of the presented pixel circuit is experimentally verified. The measured current error rates are less than 3.2% at a ΔV_TH of TFT = ±0.5 V and a ΔV_TH of OLED = 0.5 V with the emission current ranging from 7 nA to 1.13 μA.

A concrete integrated gate driver with sharing low-level-holding structure

A gate driver circuit with simplified structure is presented in this paper. The proposed design features sharing low-level-holding structure. The number of TFTs is reduced almost by 50% compared with the conventional one and the circuit is of high reliability, besides the special dummy stage is not needed by using the proposed structure.

Lifetime prediction of TFT integrated gate drivers

In this paper, we propose a method to predict the lifetime of TFT integrated gate driver circuits. Firstly, the failure analysis of the TFT circuit is performed and the maximum tolerable threshold voltage shift value (ΔVTMAX) for the low-level-holding TFTs in the integrated circuit is determined by simulations with SMARAT-SPICE. Then the dependences of threshold voltage shift (ΔVT) of TFTs on the gate bias stress are measured and the ΔVT model parameters are extracted with the measured data using linear extrapolation. Results show the proposed approach is able to fast and accurately predict the lifetime of the TFT integrated gate drivers.

A high-speed and reliable TFT integrated shift register

A high-speed and reliable TFT integrated shift register for high-resolution display is proposed. By inhibiting the leakage current in pull-up period and enhancing the discharge ability of driving TFT in pull-down period, the operating frequency is improved by 49%. Besides, the proposed circuit is expected to have high reliability due to the lowered gate voltages on the critical TFTs biased through capacitor coupling.