Zhipei Chi

Area-efficient high-speed decoding schemes for turbo decoders

Turbo decoders inherently have large decoding latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high-speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, the segmented sliding window approach and two other types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units, and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. To reduce the storage bottleneck for each subdecoder, a modified version of the partial storage of state metrics approach is presented. The new approach achieves a better tradeoff between storage part and recomputation part in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes do not cause performance degradation.

On the performance/complexity tradeoff in block turbo decoder design

In this letter, tradeoffs between very large scale integration implementation complexity and performance of block turbo decoders are explored. We address low-complexity design strategies on choosing the scaling factor of the log extrinsic information and on reducing the number of hard-decision decodings during a Chase search.

High speed VLSI architecture design for block turbo decoder

In this paper, a sub-optimal algorithm for decoding BCH (t /spl ges/ 2) turbo codes is presented. A high speed VLSI decoder architecture is proposed for codes constructed over extended GF(2/sup 5/). While the algorithm applies to higher order BCH product codes, it is shown that this particular block turbo codes, when decoded using the proposed algorithm, gives the best performance (achieving 10/sup -6/ bit error rate at a signal to noise ratio of 2.4 dB) among all two dimensional turbo product codes. Following an analysis of the impact of finite word-length effect on the performance of the SISO decoder, full parallel decoding architecture at the top level and a number of lower level high speed implementation strategies such as applying lookahead technique to reduce the critical path of the merge sort circuit and fast finite field operations are presented. Area and timing estimates obtained by logic synthesis (0.18 /spl mu/m, 1.5V CMOS technology) from VHDL descriptions are given to show how the design strategies translate into the area consumption and decoding throughput (> 32 Mbits/s.) of the VLSI implementation.

Area-efficient high speed decoding schemes for turbo/MAP decoders

Turbo decoders inherently have a large latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, two types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes introduce no performance degradation in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented.

High throughput low energy FEC/ARQ technique for short frame turbo codes

Protecting short frames using turbo coding is a challenging problem because of the short frame and the need for efficiency. In this paper, first, a scalable and easily implementable interleaver design is proposed since good random interleavers for long frame turbo codes are not guaranteed to perform well for short frames. Second, an efficient tail-biting encoding/decoding scheme is proposed, which does not sacrifice performance but significantly increases the throughput of the decoding process compared with existing methods. Finally, a novel error detection method, taking advantage a set of decoding metrics (DMs), is developed to reduce the number of cyclic redundancy check (CRC) bits used for error detection. The total savings is up to 12% for the transmission throughput and 21.5% for the energy consumption of the turbo decoder when a frame size of 49 is used.

Hybrid annihilation transformation (HAT) for pipelining QRD-based least-square adaptive filters

A novel transformation, referred to as hybrid annihilation transformation (HAT), for pipelining the QR decomposition (QRD) based least square adaptive filters has been developed. HAT provides a unified framework for the derivation of high-throughput/low-power VLSI architectures of three kinds of QRD adaptive filters, namely, QRD recursive least-square (LS) adaptive filters, QRD LS lattice adaptive filters, and QRD multichannel LS lattice adaptive filters. In this paper, HAT is presented as a solution to break the bottleneck of a high-throughput implementation introduced by the inherent recursive computation in the QRD based adaptive filters. The most important feature of the proposed solution is that it does not introduce any approximation in the entire filtering process. Therefore, it causes no performance degradation no matter how deep the filter is pipelined. It allows a linear speedup in the throughput rate by a linear increase in hardware complexity. The sampling rate can be traded off for power reduction with lower supply voltage for applications where high-speed is not required. The proposed transformation is addressed both analytically, with mathematical proofs, and experimentally, with computer simulation results on its applications in wireless code division multiple access (CDMA) communications, conventional digital communications and multichannel linear predictions.

Iterative decoding of space-time trellis codes and related implementation issues

For high data rate transmission over wireless fading channels, space-time trellis coding techniques can be employed to increase the information capacity of the communication system dramatically. In this paper, we consider the scenario of iterative decoding of concatenated space-time trellis codes and convolutional codes. Extra coding gains in addition to the diversity advantage are shown to be achieved for certain space-time trellis codes transmitted over both quasi-static and fast flat fading channels. A prestudy of related VLSI implementation issues is also presented which includes the finite word-length analysis for serial concatenated space-time trellis turbo decoders and hardware saving strategies.

Pipelined QR decomposition based multi-channel least square lattice adaptive filter architectures

QR decomposition based multi-channel least square lattice (QRD-MLSL) algorithm possesses a good numerical property and regularity which are attractive for VLSI implementation. However, due to the presence of a local recursive loop in its implementation, the algorithms speed is limited to the computation time of each computation cell. In this paper, a novel approach for pipelining the QRD-MLSL adaptive filtering algorithm is developed. The proposed architecture is pipelined at fine-grain level, thus it can be operated at arbitrarily high speed. Furthermore, it provides an exact least square solution, so there is no performance degradation. Computer simulations are presented to demonstrate the functionality of the proposed pipelining methodology.

On the better protection of short-frame turbo codes

Protecting short data frames by turbo coding is a challenging task because of the small interleaver size and the need for transmission efficiency. In this letter, turbo-decoding-metrics aided short cyclic redundancy check codes are applied to novel tailbiting encoded trellis codes with a twofold purpose: to stop the iterative decoding processes to achieve low-power design and to reduce fractional coding-rate loss. Significant coding gains can be achieved by actually increasing the transmission rate with a negligible increase in power consumption. Performance improvement is demonstrated over additive white Gaussian noise channels. The savings is up to 21.4% for the transmission throughput and 21.5% for the energy consumption of the turbo decoder when frame size 49 is used.

A study on the performance, power consumption tradeoffs of short frame turbo decoder design

Protecting short frames using turbo coding is a challenging task because of the small interleave size and the need for transmission efficiency. We explore possible trade-off between power consumption (estimated by the average number of iterations) and performance of turbo decoders when short frame turbo codes are used. Three encoding/decoding schemes are proposed to improve performance of turbo decoder in terms of frame/bit error rate, and to increase the data transmission efficiency whether ARQ protocols are performed or not. Specifically, turbo decoding metrics aided short CRC codes are applied to terminated trellis codes, tail-biting encoded trellis codes and CRC embedded trellis codes with a two-fold purpose: to stop the iterative decoding processes and to detect decoding errors at the last iteration. We show that significant coding gains can be achieved by actually increasing the coding rate with negligible increase in power consumption. Performance improvement is demonstrated over both AWGN and Rayleigh flat fading channels.