Zhiqing Geng

A 2.4-GHz Energy-Efficient Transmitter for Wireless Medical Applications

A 2.4-GHz energy-efficient transmitter (TX) for wireless medical applications is presented in this paper. It consists of four blocks: a phase-locked loop (PLL) synthesizer with a direct frequency presetting technique, a class-B power amplifier, a digital processor, and nonvolatile memory (NVM). The frequency presetting technique can accurately preset the carrier frequency of the voltage-controlled oscillator and reduce the lock-in time of the PLL synthesizer, further increasing the data rate of communication with low power consumption. The digital processor automatically compensates preset frequency variation with process, voltage, and temperature. The NVM stores the presetting signals and calibration data so that the TX can avoid the repetitive calibration process and save the energy in practical applications. The design is implemented in 0.18- μm radio-frequency complementary metal-oxide semiconductor process and the active area is 1.3 mm (2). The TX achieves 0-dBm output power with a maximum data rate of 4 Mb/s/2 Mb/s and dissipates 2.7-mA/5.4-mA current from a 1.8-V power supply for on-off keying/frequency-shift keying modulation, respectively. The corresponding energy efficiency is 1.2 nJ/b·mW and 4.8 nJ/b· mW when normalized to the transmitting power.A 2.4-GHz energy-efficient transmitter (TX) for wireless medical applications is presented in this paper. It consists of four blocks: a phase-locked loop (PLL) synthesizer with a direct frequency presetting technique, a class-B power amplifier, a digital processor, and nonvolatile memory (NVM). The frequency presetting technique can accurately preset the carrier frequency of the voltage-controlled oscillator and reduce the lock-in time of the PLL synthesizer, further increasing the data rate of communication with low power consumption. The digital processor automatically compensates preset frequency variation with process, voltage, and temperature. The NVM stores the presetting signals and calibration data so that the TX can avoid the repetitive calibration process and save the energy in practical applications. The design is implemented in 0.18- μm radio-frequency complementary metal-oxide semiconductor process and the active area is 1.3 mm 2. The TX achieves 0-dBm output power with a maximum data rate of 4 Mb/s/2 Mb/s and dissipates 2.7-mA/5.4-mA current from a 1.8-V power supply for on-off keying/frequency-shift keying modulation, respectively. The corresponding energy efficiency is 1.2 nJ/b·mW and 4.8 nJ/b· mW when normalized to the transmitting power.

A novel RFID tag chip with temperature sensor in standard CMOS process

This paper presents a novel RFID tag chip with temperature sensor in 0.18μm standard CMOS process. It consists of four blocks: RF/analog front-end circuit, 192-bit non-volatile memory (NVM), temperature sensor and digital baseband circuit. A CMOS UHF rectifier with dynamic bias using switch capacitor is proposed to improve the efficiency of rectification, while avoiding using costly Schottky diodes. We design a 192-bit NVM in standard CMOS process based on FN tunneling phenomenon with extremely small current density. It dissipates only 1.8μW/3.6μW for reading/writing operation. A 0.8μW smart temperature sensor with ±1°C resolution without power hungry ADCs is achieved. As a result, the power consumption is 5.8μW, 6.8μW, and 8.6μW for reading sensor, reading NVM and writing NVM respectively. The chip core area is 0.6mm2 in 0.18μm CMOS process.

A fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system in0.13μm CMOS

This paper proposes a sigma—delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system. With reasonable frequency planning, the system can be used in multi-standard wireless communication applications (GSM, WCDMA, GPRS, TD-SCDMA, WLAN (802.11a/b/g)). The implementation is achieved by a 0.13 μm RF CMOS process. The measured results demonstrate that three quadrature VCOs (QVCO) continuously cover the frequency from 3.1 to 6.1 GHz (65.2%), and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously. The chip was fully integrated with the exception of an off-chip filter. The entire chip area is only 3.78 mm2, and the system consumes a 21.7 mA @ 1.2 V supply without output buffers. The lock-in time of the PLL frequency synthesizer is less than 4 μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory (NVM) can store the digital configuration signal of the system, including presetting signals to avoid the calibration process case by case.

A low power compact CMOS programmable temperature switch with process compensation

A low power compact CMOS programmable temperature switch with process compensation is presented. Its threshold temperature Tth can be programmed by a digital signal. The operating principle of the temperature switch is theoretically explained. We adopt a simple circuit architecture and a subthreshold CMOS circuit technique to reduce the chip size and the power consumption. A process compensation circuit is designed to compensate the threshold temperature Tth variation automatically. The switch circuit is implemented in a standard 0.18um CMOS process. The measured results show that the temperature switch can be programmed to perform the switch operation at 12 different threshold temperature Tths from 45°C–100°C with a 5°C increment. The chip core area is 0.03mm2 and the power consumption is less than 1uA at 1.8V power supply.

Effective behavioral models for ΣΔ Fractional-N Frequency Synthesize phase noise prediction

A methodology is presented for predicting the phase noise of the ΣΔ Fractional-N Frequency Synthesize that is both accurate and efficient based on sampling the noise voltage in the time domain. An accurate Voltage Control Oscillator (VCO) noise model is presented, including both thermal noise and 1/f noise. The behavioral model provides a great speed-up over the transistor level simulation and an accurate phase noise prediction.

A novel 0.72–6.2GHz continuously-tunable ΔΣ fractional-N frequency synthesizer

This paper presents a wideband ΔΣ-based fractional-N synthesizer with three integrated quadrature VCOs for multiple-input multiple-output (MIMO) wireless communication applications. It continuously covers a wide range frequency from 0.72GHz to 6.2GHz that is suitable for multiple communication standards. The synthesizer is designed in 0.13-um RF CMOS process. The dual clock full differential multi-modulus divide (MMD) with low power consumption can operate over 9GHz under the worst condition. In the whole range frequency from 0.72GHz to 6.2GHz, the maximal tuning range of the QVCOs reaches 33.09% and their phase noise is −119dB/Hz∼−124dB/Hz @1MHz. Its current is less than 12mA at a 1.2V voltage supply when it operates at the highest frequency of 6.2GHz.