Zhu Can

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology

A 2-Gsample/s 8-b analog-to-digital converter in 0.35 μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS. Digital calibration technology is used for the offset and gain corrections of the S/H circuit, the offset correction of preamplifier, and the gain and clock phase corrections between channels. As a result of testing, the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

A Digital Offset Self-Calibration Technique for 3-Bit Flash Converter of an Ultra High-Speed Folding and Interpolating ADC

This paper proposed a digital offset self-calibration technique for the flash converter of an ultra high-speed folding and interpolating ADC. The chip is processed in 0.18-µm CMOS technology. The measured results show that the digital calibration technique can efficiently improve the ADC characteristics.

An ultra high-speed 8-bits analog-to-digital converter design

In this paper, an ultra high-speed 8-bits analog-to-digital converter with digital foreground calibration in 0.18-µm CMOS technology is presented. The spice simulation and the measured results show the folding and interpolating ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration Enabled at Nyquist.

Linearity improvement base on digital foreground calibration algorithm for a ultra high-speed analog-to-digital converter

In this paper, a digital calibration algorithm for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-fin CMOS technology is presented. The spice simulation result shows the digital foreground calibration algorithm can efficiently improve the linearity of the ADC.

Digital calibration implementation for track-and-hold offset in a high-speed timing-interleaved folding and interpolating analog-to-digital converter

A digital calibration implementation for track-and-hold offset in a high-speed timing-interleaved folding and interpolating analog-to-digital converter is proposed in this paper. The spice simulation and measured results both show that the digital calibration technique can efficiently cancel the T/H offset and improve the linearity of the ADC.