Zhuo Wang

18.4 A matrix-multiplying ADC implementing a machine-learning classifier directly with data conversion

Embedded sensing systems conventionally perform A-to-D conversion followed by signal analysis. In many applications, the analysis of interest is inference (e.g., classification), but the sensor signals involved are too complex to model analytically. Machine learning is gaining prominence because it enables data-driven training of classifiers, overcoming the need for analytical models. This work presents: 1) an algorithmic formulation, where feature extraction and classification are combined into a single matrix, reducing the total multiplications needed, and 2) a matrix-multiplying ADC (MMADC) that enables multiplication of input samples by a programmable matrix. Thus, the MMADC combines feature extraction and classification with data conversion, mitigating the need for further computations. Two systems are demonstrated: an ECG-based cardiac-arrhythmia detector and an image-pixel-based gender detector.

Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels

We present an approach for overcoming computational errors at run time that originate from static hardware faults in digital processors. The approach is based on embedded machine-learning stages that learn and model the statistics of the computational outputs in the presence of errors, resulting in an error-aware model for embedded analysis. We demonstrate, in hardware, two systems for analyzing sensor data: 1) an EEG-based seizure detector and 2) an ECG-based cardiac arrhythmia detector. The systems use a small kernel of fault-free hardware (constituting <;7.0% and <;31% of the total areas respectively) to construct and apply the error-aware model. The systems construct their own error-aware models with minimal overhead through the use of an embedded active-learning framework. Via an field-programmable gate array implementation for hardware experiments, stuck-at faults are injected at controllable rates within synthesized gate-level netlists to permit characterization. The seizure detector demonstrates restored performance despite faults on 0.018% of the circuit nodes [causing bit error rates (BERs) up to 45%], and the arrhythmia detector demonstrates restored performance despite faults on 2.7% of the circuit nodes (causing BERs up to 50%).

16.2 A large-area image sensing and detection system based on embedded thin-film classifiers

This paper presents a large-area image sensing and detection system that integrates, on glass, sensors and thin-film transistor (TFT) circuits for classifying images from sensor data. Large-area electronics (LAE) enables the formation of millions of sensors spanning physically large areas; however, to perform processing functions, thousands of sensor signals must be interfaced to CMOS ICs, posing a critical limitation to system scalability. This work presents an approach whereby image detection of shapes is performed using simple circuits in the LAE domain based on amorphous silicon (a-Si) TFTs. This reduces the interfaces to the CMOS domain. The limited computational capability of TFT circuits as well as high variability and high density of process defects affecting TFTs and sensors is overcome using a machine-learning algorithm known as error-adaptive classifier boosting (EACB) to form embedded weak classifiers. Through EACB, we show that high-dimensional sensor data from a-Si photoconductors can be reduced to a small number of weak-classifier decisions, which can then be combined in CMOS to achieve strong-classifier performance. For demonstration, a system classifying five shapes achieves performance of >85%/>95% [true-positive (tp)/true-negative (tn) rates] [near the level of an ideal software-implemented support vector machine (SVM) classifier], while the total number of signals from 36 sensors in the LAE domain is reduced by

Error-adaptive classifier boosting (EACB): Exploiting data-driven training for highly fault-tolerant hardware

3.5\text{-}9\times

Error Adaptive Classifier Boosting (EACB): Leveraging Data-Driven Training Towards Hardware Resilience for Signal Inference

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A machine-learning classifier implemented in a standard 6T SRAM array

Technological scaling and system-complexity scaling have dramatically increased the prevalence of hardware faults, to the point where traditional approaches based on design margining are becoming un-viable. The challenges are exacerbated in embedded sensing applications due to constraints on system resources (energy, area). Given the importance of classification functions in such applications, this paper presents an architecture for overcoming faults within a classification processor. The approach employs machine learning for modeling not only complex sensor signals but also error manifestations due to hardware faults. Adaptive boosting is exploited in the architecture for performing iterative data-driven training. This enables the effects of faults in preceding iterations to be modeled and overcome during subsequent iterations. We demonstrate a system integrating the proposed classifier, capable of training its model entirely within the architecture by generating estimated training labels. FPGA experiments show that high fault rates (affecting >3% of all circuit nodes) occurring on >80% of the hardware can be overcome, restoring system performance to fault-free levels.

A Large-Area Image Sensing and Detection System Based on Embedded Thin-Film Classifiers

The continued scaling of CMOS technologies and consideration of post-CMOS technologies has elevated hardware reliability to a first-class challenge, particularly in energy- and resource-constrained embedded sensor applications. In such applications, there is an increasing emphasis on inference functions. Machine-learning algorithms play an important role by enabling the construction of data-driven models for inference over data that is too complex to model analytically. This paper explores how data-driven training can be exploited to also overcome computational errors due to hardware faults within an inference stage. FPGA emulation with randomized fault injections shows that the proposed architecture restores system performance to the level of a fault free system, with 1% of the hardware requiring explicit fault protection, and with digital faults affecting >2% of the circuit nodes in the rest of the hardware. To train an error-aware inference model, a training algorithm is presented whose hardware (memory) and energy requirements are reduced by 65 × and 10 × compared to previously reported algorithms (AdaBoost and FilterBoost respectively), thereby enabling model construction entirely on the device.

Realizing Low-Energy Classification Systems by Implementing Matrix Multiplication Directly Within an ADC

This paper presents a machine-learning classifier where the computation is performed within a standard 6T SRAM array. This eliminates explicit memory operations, which otherwise pose energy/performance bottlenecks, especially for emerging algorithms (e.g., from machine learning) that result in high ratio of memory accesses. We present an algorithm and prototype IC (in 130nm CMOS), where a 128×128 SRAM array performs storage of classifier models and complete classifier computations. We demonstrate a real application, namely digit recognition from MNIST-database images. The accuracy is equal to a conventional (ideal) digital/SRAM system, yet with 113× lower energy. The approach achieves accuracy >95% with a full feature set (i.e., 28×28=784 image pixels), and 90% when reduced to 82 features (as demonstrated on the IC due to area limitations). The energy per 10-way digit classification is 633pJ at a speed of 50MHz.

Reducing quantization error in low-energy FIR filter accelerators

Large-area electronics (LAE) enables the formation of a large number of sensors capable of spanning dimensions on the order of square meters. An example is X-ray imagers, which have been scaling both in dimension and number of sensors, today reaching millions of pixels. However, processing of the sensor data requires interfacing thousands of signals to CMOS ICs, because implementation of complex functions in LAE has proven unviable due to the low electrical performance and inherent variability of the active devices available, namely amorphous silicon (a-Si) thin-film transistors (TFTs) on glass. Envisioning applications that perform sensing on even greater scales, this work presents an approach whereby high-quality image detection is performed directly in the LAE domain using TFTs. The high variability and number of process defects affecting both the TFTs and sensors are overcome using a machine-learning algorithm known as Adaptive Boosting (AdaBoost) [1] to form an embedded classifier. Through AdaBoost, we show that high-dimensional sensor data can be reduced to a small number of weak-classifier decisions, which can then be combined in the CMOS domain to generate a strong-classifier decision.

Enabling hardware relaxations through statistical learning

In wearable and implantable medical-sensor applications, low-energy classification systems are of importance for deriving high-quality inferences locally within the device. Given that sensor instrumentation is typically followed by A-D conversion, this paper presents a system implementation wherein the majority of the computations required for classification are implemented within the ADC. To achieve this, first an algorithmic formulation is presented that combines linear feature extraction and classification into a single matrix transformation. Second, a matrix-multiplying ADC (MMADC) is presented that enables multiplication between an analog input sample and a digital multiplier, with negligible additional energy beyond that required for A-D conversion. Two systems mapped to the MMADC are demonstrated: (1) an ECG-based cardiac arrhythmia detector; and (2) an image-pixel-based facial gender detector. The RMS error over all multiplication performed, normalized to the RMS of ideal multiplication results is 0.018. Further, compared to idealized versions of conventional systems, the energy savings obtained are estimated to be 13× and 29×, respectively, while achieving similar level of performance.