Ziyi Hu

Theory and verification of operator design methodology

Non-recurring-engineering (NRE) and time-to-market play an increasingly important role in the field of IC design. Meanwhile, with the continuous development of IC manufacturing technology, it is necessary to propose a novel design methodology to shorten design cycle and enhance design efficiency. In this paper, operator design methodology (ODM) is presented and an H.264 encoder is implemented as a verification. According to the flow of ODM, the register transfer level (RTL) design of H.264 encoder has been accomplished with 15 manmonths, which is lower than the average 19 man-months in the field of traditional application specific integrated circuit (ASIC) design. Moreover, with the advantage of operator design library, the design has a comparable performance with other ASIC implementations. The obtained design can support a real-time video encoding of 720p at 60 frames per second or 1080p at 30 frames per second, working at 167 MHz with SMIC 0.13 μm CMOS technology. These results provide good evidence for the practicability and efficiency of ODM.

Implementation of intra prediction in H.264 based on a novel design methodology

A novel IC design methodology, named Operator Methodology (OM), is proposed in this paper and has been applied to intra prediction of H.264 entropy coding, satisfying the need of 1080P@30pfs performance. This new methodology will map the high-level language, such as C programming language, to verilog HDL through a special middle language, using a series of analysis processes like time-noting and optimization. The implementation of intra prediction in H.264 by OM, which is verified to work at 100MHZ in a Xilinx Virtex6 FPGA and 0.13um SMIC CMOS technology at 167MHz frequency, shows that OM can speed up IC design effectively and obtain comparable performance with other ASIC results. Finally, our design cycle, measured by man-month, will be decreased by a large scale using auto-translator and auto-optimizer.

A hardware efficient implementation of chroma interpolator for H.264 encoders

In this paper, an implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders is proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements which are comprised of only adders. The design was prototyped within a Xilinx Virtex6 FPGA at 245 MHz. The design was also synthesized with SMIC 130ns CMOS technology at 200 MHz, which can support a real-time HDTV application.

Scheduling to timing optimization for a novel high-level synthesis approach

Traditional IC design methodology based on standard cells shows its limitation on design efficiency, which can not satisfy the needs for shorter time-to-market and more advanced functionality of IC products. To solve this problem, a novel high level synthesis method named operator design method is proposed. In this paper, a scheduling scheme to timing optimization for operator design method is proposed, which is carried out based on the attributes of the operand in the operation and dependence of the operations. The experiment results proves the feasibility and the efficiency of the operator design method, and obtains a 65% faster data-processing capacity and 30% reduction in hardware cost than that of SPARK tool of University California at San Diego.

A NOVEL DECOMPOSITION APPROACH AND VLSI IMPLEMENTATION OF CHROMA INTERPOLATOR FOR H.264 ENCODERS

In this paper, a novel decomposition approach and VLSI implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders are proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements (AEs) which are comprised of only adders. Four types of AEs are developed and a pipelining hardware design is proposed to conduct the chroma interpolation with great hardware reuse. The proposed design was prototyped within a Xilinx Virtex6 XC6VLX240T FPGA with a clock frequency as high as 245 MHz. The proposed design was also synthesized with SMIC 130 nm CMOS technology with a clock frequency of 200 MHz, which could support a real-time HDTV application with less hardware cost and lower power consumption.

Generation of memory architecture in operator design methodology

Nowadays, traditional ASIC design methodology shows its limitations to meet the short time-to-market which is the hallmark of modern consumer electronic products, and great interests have been focused on high-level synthesis (HLS) in the past two decades. In this paper, the scheme for generation of the memory architecture in a novel HLS method named operator design methodology is proposed. The principle and process of operator design methodology is first presented, then the steps of mapping the data array and pointer in C description to the memory model in hardware description is demonstrated, finally a hardware implementation of a target algorithm is conducted based on the proposed memory generation scheme and the experiment results is compared with that of the SPARK tool by UC San Diego, which presents an 65% increase in the performance and 30% reduction in hardware cost under the constraint of 100MHz clock frequency.

Operator Design Methodology and Implementation of Intra Prediction in H.264 Encoder

Operator design methodology is proposed in this chapter and has been applied to the intra prediction of the H.264 encoder with HDTV performance of 1080P@30fps. This novel idea and approach will take the place of the traditional IC design methodology using standard cells, gate array, and reused IP. It will map the high-level language to verilog HDL/VHDL through a special language, guided by the conception of high-level synthesis (HLS). The result of the proposed structure can easily be applied to other video encoder/decoder applications and has been verified to work at 88.7 MHZ in a Xilinx Virtex6 FPGA and in 0.13 µ SMIC CMOS technology at 167 MHz frequency, and has also shown great competitive performance in both performance and design speed. Besides, our design time, measured by man-month, will be decreased by a large scale using our autotranslator and autooptimizer later.