Zohreh Kiaee

Thermal Stress Effects on the Electrical Properties of p-Channel Polycrystalline-Silicon Thin-Film Transistors Fabricated via Metal-Induced Lateral Crystallization

We developed a method to compact the glass sheets of a flat-panel displays that use metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs), and the effects of thermal stress on the fabricated devices were compared against those of a bare-glass device. The glass substrate was exposed to a temperature of 650 °C for 40 h in order to suppress the glass shrinkage to 0.01 ppm, which suitable for a MILC poly-Si TFT process. The compressive strain that originates from glass shrinkage generally increases the size of the micro-cracks and the vacancies, and as a result, most of the electrical parameters of a bare glass device (such as the on-current, off-current, field-effect mobility, subthreshold slope, and threshold voltage) had a higher level of degradation than those of the device with the compacted glass. The increase in the on-current and the field-effect hole mobility under the compressive strain for poly-Si TFTs showed a similar behavior to that of single-crystalline-silicon (c-Si) TFTs under compressive strain. However, the increase in the off-current was the converse of that of strained c-Si TFT.

Multibit ferroelectric field-effect transistor with epitaxial-like Pb(Zr,Ti)O3

Being able to control grain boundaries during the phase transformation when processing a ferroelectric thin-film is crucial for the successful development of practical multibit ferroelectric memory. A novel development of ferroelectric thin-film crystallization processing for realizing epitaxial-like single crystals via artificial nucleation by Pt-seeding is reported here. Dividing the nucleation and growth mechanism by Pt-seeding, it is possible to obtain large and uniform rectangular-shaped ferroelectric grains, large enough to fabricate a field-effect transistor (FET) in the inside of the crystal grain. The fabricated ferroelectric FET, Pt/Pb(Zr,Ti)O3/ZrTiO4/Si, showed a large memory window (∼2.2 V), a low operation voltage (∼6 V), and an ultra-fast program/erase speed (∼10−6 s). Moreover, there was no degradation after 1015 cycles of bipolar fatigue testing and the sample even showed a long retention time after 1 yr. All of these characteristics correspond to the best performance among all types of fe...

Integrating Epitaxial-Like Pb(Zr,Ti)O3 Thin-Film into Silicon for Next-Generation Ferroelectric Field-Effect Transistor.

The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form randomly. Controlling the nature of nucleation and growth are the keys to achieving a good crystalline thin-film. However, the sought after high-quality ferroelectric thin-film has so far been thought to be impossible to make, and research has been restricted to atomic-layer deposition which is extremely expensive and has poor reproducibility. Here we demonstrate a novel epitaxial-like growth technique to achieve extremely uniform and large rectangular-shaped grains in thin-film ferroelectrics by dividing the nucleation and growth phases. With this technique, it is possible to achieve 100-μm large uniform grains, even made available on Si, which is large enough to fabricate a field-effect transistor in each grain. The electrical and reliability test results, including endurance and retention test results, were superior to other FeRAMs reported so far and thus the results presented here constitute the first step toward the development of FeRAM using epitaxial-like ferroelectric thin-films.

Characterization of Lateral Structure of the p–i–n Diode for Thin-Film Silicon Solar Cell

The lateral structure of the p-i-n diode was characterized for thin-film silicon solar cell application. The structure can benefit from a wide intrinsic layer, which can improve efficiency without increasing cell thickness. Compared with conventional thin-film p-i-n cells, the p-i-n diode lateral structure exploited direct light irradiation on the absorber layer, one-side contact, and bifacial irradiation. Considering the effect of different carrier lifetimes and recombinations, we calculated efficiency parameters by using a commercially available simulation program as a function of intrinsic layer width, as well as the distance between p/i or n/i junctions to contacts. We then obtained excellent parameter values of 706.52 mV open-circuit voltage, 24.16 mA/Cm2 short-circuit current, 82.66% fill factor, and 14.11% efficiency from a lateral cell (thickness = 3 μm; intrinsic layer width = 53 μm) in monofacial irradiation mode (i.e., only sunlight from the front side was considered). Simulation results of the cell without using rear-side reflector in bifacial irradiation mode showed 11.26% front and 9.72% rear efficiencies. Our findings confirmed that the laterally structured p-i-n cell can be a potentially powerful means for producing highly efficient, thin-film silicon solar cells.

Advanced Four-Mask Process Bottom-Gate Poly-Si TFT via Self-Aligned NiSi 2 Seed-Induced Lateral Crystallization

We report on a method to fabricate high-performance bottom-gate poly-Si (BGPS) thin-film transistors (TFTs) with a four-mask process via self-aligned (SA) NiSi2 seed-induced lateral crystallization (SILC). Previously, the BGPS TFT crystallized by SILC was reported to have high electrical performance with a simple process. However, this approach still requires an additional mask for lateral crystallization, making the process more complicated and expensive. In this letter, by using the SA-SILC method, only a few NiSi2 seeds reach the intrinsic Si surface through the side edges of the etch stopper and then crystallize the channel. This SA-SILC enables low metal contamination by a few seeds in the channel, shorter annealing time due to reduced length for SILC, and a simple four-mask process. The SA-SILC BGPS TFTs exhibited a steep subthreshold slope of 0.16 Vdecade-1, a high field-effect mobility of 230 cm2V-1s-1, and kink-free output characteristics.

Tempered glass substrate effect on the growth of polycrystalline-silicon and its applications for reliable thin-film transistors

In this work, we investigated a novel mechanism of polycrystalline-silicon (poly-Si) grown on tempered glass and the stability under various bias-stress effects in the performance of poly-Si thin-film transistors (TFT) fabricated on tempered glass and compared with the poly-Si TFT on bare glass. The glass shrinkage, mask misaligned width, and thermal strain of the tempered glass were 0.01 ppm, 0.9 μm, and 26.1 MPa. The compressively tensioned bare glass showed a suppression of the crystallization rate showing a small grains, whereas the tempered glass showed high crystallization rate showing a large grains. The thermal substrate stress effect on the poly-Si TFT showed serious reliability degradation, while the poly-Si TFT on tempered glass showed stable driving characteristics on the gate and hot-carrier bias stress. The better stability is due to the smooth surface and non microcracks of poly-Si on tempered glass, which is about 1.5 nm that is much smaller than that (5 nm) of a poly-Si on bare glass.

Compressive Stressed P-Channel Polycrystalline-Silicon Thin-Film Transistors for High Field-Effect Mobility

A compressively stressed polycrystalline-silicon (poly-Si) thin-film transistor (TFT) was successfully demonstrated on a tensile stressed glass substrate. The layer of a-Si:H/bare glass was annealed for 45 h with a sharp annealing and a slow cooled condition in order to form compressive strain on the a-Si:H film. Then, the a-Si:H was crystallized by NiSi2 seed-induced lateral crystallization having (110) preferred texture, and the top-gated TFT was fabricated. The electrical properties were excellent comparing with the strain-free poly-Si TFT, and especially the field-effect mobility increased 9.3 times higher.

50-nm Nano-Scaled Vertical-Transistor with NiSi2 Seed-Induced Vertically Crystallized Poly-Silicon Channel for Very-Large-Scale-Integration

Vertical-channel MOSFETs are hard to demonstrate a high electrical performance than the planar MOSFETs because of its polycrystalline-silicon (poly-Si) channel for 3-D CMOS ICs. In this paper, we have demonstrated a vertical poly-silicon-channel (VPSC) transistor NiSi2 seed-induced vertical crystallization (SIVC) and compared with the typical SG-VPC MOSFETs with solid-phase crystallization (SPC). The SIVC poly-Si showed large longitudinal grains with low defect trap sites, while the SPC poly-Si showed small spherical grains with large defect trap sites. Therefore, the electrical performance of SG-VPC MOSFETs with SIVC was superior to the SG-VPC MOSFETs with SPC in all aspects.

Fabrication and characterization of lateral P-I-N poly-Si solar cell utilizing Ni silicide-induced crystallization on glass substrate

We prepared a lateral structure of thin-film polycrystalline (Poly-Si) solar cell by low temperature Ni silicide-induced crystallization (SIC) for the first time. We compared I-V characteristics of two types of lateral Solar cells (LSCs), with isolated (p-i-n) cells and connected (p-i-n) cells. The LSCs of isolated cells showed clear rectifying behavior for a wider range of intrinsic region width (W) compared to the connected cells. At the same values of W, a higher short-circuit current (JSC) was obtained from isolated cells than the connected cells. We obtained JSC of 3.3 mA/cm2 and an open-circuit voltage (VOC) of 0.13 V from a relatively thin ~400 nm isolated cell, without applying any optimization.

Retraction Note to: Retraction: Integrating Epitaxial-Like Pb(Zr,Ti)O3 Thin-Film into Silicon for Next-Generation Ferroelectric Field-Effect Transistor

The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form randomly. Controlling the nature of nucleation and growth are the keys to achieving a good crystalline thin-film. However, the sought after high-quality ferroelectric thin-film has so far been thought to be impossible to make, and research has been restricted to atomic-layer deposition which is extremely expensive and has poor reproducibility. Here we demonstrate a novel epitaxial-like growth technique to achieve extremely uniform and large rectangular-shaped grains in thin-film ferroelectrics by dividing the nucleation and growth phases. With this technique, it is possible to achieve 100-μm large uniform grains, even made available on Si, which is large enough to fabricate a field-effect transistor in each grain. The electrical and reliability test results, including endurance and retention test results, were superior to other FeRAMs reported so far and thus the results presented here constitute the first step toward the development of FeRAM using epitaxial-like ferroelectric thin-films.