Zoltán Nagy

Evaluation of the brain network organization from EEG signals: a preliminary evidence in stroke patient.

Synchronous brain activity in motor cortex in perception or in complex cognitive processing has been the subject of several studies. The advanced analysis of cerebral electro‐physiological activity during the course of planning (PRE) or execution of movement (EXE) in a high temporal resolution could reveal interesting information about the brain functional organization in patients following stroke damage. High‐power (128 channels) electroencephalography registration was carried out on 8 healthy subjects and on a patient with stroke with capsular lacuna in the right hemisphere. For activation of motor cortex, the finger tapping paradigm was used. In this preliminary study, we tested a theoretical graph approach to characterize the task‐related spectral coherence. All of the obtained brain functional networks were analyzed by the connectivity degree, the degree distribution, and efficiency parameters in the Theta, Alpha, Beta, and Gamma bands during the PRE and EXE intervals. All the brain networks were found to hold a regular and ordered topology. However, significant differences (P < 0.01) emerged between the patient with stroke and the control subjects, independently of the neural processes related to the PRE or EXE periods. In the Beta (13–29 Hz) and Gamma (30–40 Hz) bands, the significant (P < 0.01) decrease in global‐ and local‐efficiency in the patients networks, reflected a lower capacity to integrate communication between distant brain regions and a lower tendency to be modular. This weak organization is principally due to the significant (P < 0.01 Bonferroni corrected) increase in disconnected nodes together with the significant increase in the links in some other crucial vertices. Anat Rec, 292:2023–2031, 2009.

Implementation of Nonlinear Template Runner Emulated Digital CNN-UM on FPGA

In the original CNN paradigm template values are defined as constants but several complex tasks can be efficiently solved by using nonlinear weights between the CNN cells. Unfortunately programmable nonlinear weights can not be implemented by using present day analog VLSI technology. In this paper a new emulated digital CNN-UM architecture will be presented which makes it possible to use zero and first order nonlinear templates during emulation. The new architecture is based on the Falcon emulated digital CNN-UM architecture and implemented on FPGAs. The computing precision of the architecture is configurable and the area/speed/accuracy tradeoffs are investigated

Acoustic wvave propagation modeling on 3D CNN-UM architecture

Solution of partial differential equations (PDE) has long been one of the most important fields of mathematics. Several previous studies proved the effectiveness of the CNN-UM solution for partial differential equations in two dimensions. This paper works with the 3D acoustic wave equation which describes the pressure wave propagation in fluid medium. This three-dimensional PDE can be solved also with 3D CNN-UM and multilayer 2D CNN-UM architecture. Unfortunately the huge number of space-dependent equations and the low computational precision do not make it possible to utilize the huge computing power of the analogue CNN-UM chips so the Falcon emulated digital CNN-UM architecture is used to implement our solution

An embedded CNN-UM Global Analogic Programming Unit implementation on FPGA

In this paper the implementation of an embedded GAPU (global analogic programming unit) on the reconfigurable emulated digital CNN-UM architecture will be presented. It has been extended by a Xilinx MicroBlaze soft processor core to take full advantage of the joint computing power of high speed distributed arithmetics and programmability. The basic guidelines are presented considering the design of embedded GAPU with special regards to speed, programming flexibility and minimal additional cost in area

Methods to highlight consistency in repeated EEG recordings

Abstract In the present work, we aimed to find subject related features in EEG recordings which are consistent through multiple recordings and apply them in biometry. Essentially to use the brains electroencephalographic activity as a possible way to identify individuals. Seventeen healthy subjects participated in the study and their brain activity were recorded through a 56 EEG channel, high-density EEG cap during one minute of resting state with eyes open and/or eyes closed. The subjects were participating in a second recording session as well, thus creating a dataset of ten closed and ten open eyed recordings each with follow-up measurements. Analyzing results of various testing scenarios involving power spectrum density (PSD), coherence (COH), and the imaginary part of coherence (iCOH) on segments of ten seconds, we concluded the best parameter setup as well as a minimal set of electrodes and the best possible feature vector assembly based on these computations. By using a naive Bayes classifier and K-fold cross-validations, we observed the highest correct recognition rates (CRR 98.33%) during eyes closed resting state at the parieto-occipital-temporal electrodes, suggesting these as the most stable characteristics therefore the most suitable, among those investigated here, for identifying individuals.

FPGA-based simulation of 3D light propagation

In this paper, we describe how to emulate 3D wave dynamics on a 2D FPGA-based architecture. The algorithm is based on the Paraxial Helmholtz Equation: which describes the beam propagation through different media with different refractive indices. To solve this wave propagation equation numerically the FPGA-accelerated hardware operates with spatially varying templates. The FPGA-based wave-equation solver is very well parallelizable, so the resulting algorithm will also be amenable to mega-core architectures.

Emulating optically inspired massively parallel non-Boolean operators on FPGA

In this paper, we demonstrate two optically inspired massively parallel non-Boolean operators running on FPGA. One of the algorithm is based on the Paraxial Helmholtz Equation: which describes the beam propagation through different media with different refractive indices, and the other is based on the concepts of optical computing: quasi-optical wave equations are solved numerically, using FPGA-accelerated hardware. The second algorithm describes a holographic pattern-matching algorithm. Both of the two FPGA-based implementations are very well parallelizable, consequently they are also be amenable to mega-core architectures.

FPGA implementation of a foveal image processing system for UAV applications

An on-board UAV high-performance collision avoidance system sets up drastic constraints, which can be fulfilled by using carefully optimized many-core computational architectures. In this demonstration we introduce a many-core processor system, which can process a 150 megapixels/sec video flow to identify remote airplanes. The introduced processor system is implemented on Xilinx Spartan-6 and Zynq SoC FPGAs, and consumes less than 1W.

Computational fluid flow simulation on body fitted mesh geometry with FPGA based emulated digital cellular neural networks

The analog CNN-UM can be used to solve the Navier-Stokes equations quite fast. But using in engineering applications it can not be sufficiently accurate and reliable because noises from the environment, such as power supply noise or temperature fluctuation. With the proper Field Programmable Gate Array (FPGA) we can gain sufficient (adequate) computation speed with high precision. The dedicated hardware elements of the FPGA can highly accelerate the computations on curved surface. Consequently it can be used in industrial applications where fluid flow simulation around complex shapes is required. In the paper the implementation and optimization of a new Computational Fluid Dynamics (CFD) solver architecture, which can work on Body Fitted Mesh geometry, on FPGA is described. The proposed new architecture is compared to existing solutions in terms of area, speed, accuracy and power dissipation.

A CNN motivated array computing model

Approaching the limits of scaling down of CMOS circuits where transistors can switch faster and faster transmitting information between different areas of an integrated circuit has great importance. The speed of signals are determined by the physical properties of the medium therefore the distance between the elements should be decreased to improve performance. Array processors are a good candidate to solve this problem. Similar approach is required on today high performance field programmable logic devices where wire delay dominates over gate (LUT) delay. Centralized control unit of a configurable accelerator might become a performance bottleneck on the current state-of-the-art FPGAs. In the paper a process network inspired approach is given to create distributed control units. The advantage of the proposed method will be shown by designing a complex multi-layer array computing architecture to emulate the operation of a mammalian retina in real time.