Zsolt Vörösházi

Emulated digital CNN-UM solution of partial differential equations

We present here new cellular neural/non-linear networks (CNN)-based emulated digital architectures specifically designed for the solution of different partial differential equations (PDE). The array structure and local connectivity of the CNN paradigm make it a natural framework to describe the behaviour of locally interconnected dynamical systems. Solution of the PDE is carried out by a spatio-temporal dynamics, which can be computed in real-time on analogue CNN-UM chips, but the accuracy of the solution is low. Additionally, solution of PDEs on a CNN-UM architecture often requires a multi-layer structure and non-linear templates which is partially or not supported on the current analogue VLSI CNN-UM chips. To overcome these obstacles while preserving high computing performance a configurable emulated digital CNN-UM can be used where the main parameters (accuracy, template size and number of layers) are configurable. Additionally, the symmetry of the finite difference operators makes it possible to specialize the emulated digital CNN-UM architecture to solve a specific type of PDE, which results in higher performance. Emulated digital CNN-UM processors use fixed-point numbers to carry out computations, and by decreasing the precision the speed of the computations can be improved. Hence, a simple algorithm is introduced to determine the optimal fixed-point precision and maximize computing performance. Copyright

An advanced emulated digital retina model on FPGA to implement a real-time test environment

This paper presents an extended emulated digital retina model to compute two different retina channels in video real-time. The proposed emulated digital implementation of the two-channel retina model was compared to the previously developed single channel model from three different points of view: processing speed, number of physical cells and accuracy. A real-time test environment with camera input and display output is going to be set up to analyze the retina model implementation on emulated digital CNN (cellular neural/nonlinear network) model by using a 6M gate equivalent FPGA (field programmable gate array)

FPGA-based real time, multichannel emulated-digital retina model implementation

The function of the low-level image processing that takes place in the biological retina is to compress only the relevant visual information to a manageable size. The behavior of the layers and different channels of the neuromorphic retina has been successfully modeled by cellular neural/nonlinear networks (CNNs). In this paper, we present an extended, application-specific emulated-digital CNN-universal machine (UM) architecture to compute the complex dynamic of this mammalian retina in video real time. The proposed emulated-digital implementation of multichannel retina model is compared to the previously developed models from three key aspects, which are processing speed, number of physical cells, and accuracy. Our primary aim was to build up a simple, real-time test environment with camera input and display output in order to mimic the behavior of retina model implementation on emulated digital CNN by using low-cost, moderate-sized field-programmable gate array (FPGA) architectures.

FPGA based emulated-digital CNN-UM implementation with GAPU

The paper addresses the issue of implementing a GAPU (global analogic programming unit) on the emulated-digital CNN-UM (cellular neural/nonlinear networks universal machine) architecture. It has been embedded with a flexible Xilinx MicroBlaze soft-core processor to take full advantage of the joint computing power of high-speed arithmetics and programmability. The GAPU implementation accelerates the processing performance of the Falcon architecture by decreasing the I/O communication and it also provides a stand-alone operation, which is capable of controlling complex sophisticated analogic CNN algorithms similar to various visual microprocessors, such as the ACE16k and the Q-Eye in the Bi-i, and eye-RIS cellular vision systems. Our primary aim was to implement an FPGA-based emulated-digital CNN-UM with embedded GAPU for computation intensive, real image-processing tasks.

An embedded CNN-UM Global Analogic Programming Unit implementation on FPGA

In this paper the implementation of an embedded GAPU (global analogic programming unit) on the reconfigurable emulated digital CNN-UM architecture will be presented. It has been extended by a Xilinx MicroBlaze soft processor core to take full advantage of the joint computing power of high speed distributed arithmetics and programmability. The basic guidelines are presented considering the design of embedded GAPU with special regards to speed, programming flexibility and minimal additional cost in area

Investigation of area and speed trade-offs in FPGA implementation of an image correlation algorithm

In this paper an image correlation algorithm is implemented on FPGA architecture for assisted movements of visually impaired persons or automotive driving systems. Taking into account the limitations of FPGA devices and the special requirements of the correlation based image matching algorithm a semi-parallel approach is proposed. This provides an optimal tradeoff between area and speed of the implemented algorithm. Several key issues are investigated and discussed related to the speed and area.

A standalone FPGA based emulated-digital CNN-UM system

The Falcon emulated-digital CNN-UM (cellular neural/nonlinear networks universal machine) architecture has been extended by an embedded GAPU (global analogic programming unit) using the flexible Xilinx MicroBlaze soft-core processor to take full advantage of the joint computing power of high-speed distributed arithmetics and programmability. The implemented GAPU provides a stand-alone operation, which is capable of controlling complex sophisticated CNN analogic algorithms similar to various visual microprocessors, such as the ACE4k, ACE16k, and Bi-i vision systems. The quality of the embedded GAPU implementation is demonstrated by analogic algorithms, mainly in which sequences of template operations are required.

A modular test platform for real-time measurement and analysis of EMG signals for improved prosthesis control

A hardware platform for real-time measurement and analysis of human electromyographic signals (EMG) is proposed. The system is designed to have modular structure to facilitate further integration of various measurement, signal processing and actuator control tasks. To assess reachable system performance in the target application of EMG classification, two different classification methods are tested on the Xilinx Zynq-7000 All Programmable SoC using offline recorded multichannel lower arm muscle signals.

An advanced real-time, multi-channel emulated-digital retina model implementation on FPGA

Various channels of the neuromorphic, multi-layer retina has been successfully modeled by CNN. Our primary aim was to build up a real-time test environment with camera input and display output in order to mimic the behavior of retina model implementation on emulated digital CNN by using a low-cost, moderate sized field-programmable gate array (FPGA) architecture.

A Real-time Mammalian Retina Model Implementation on FPGA

This paper presents an extended emulated digital retina model to compute two different retina channels in video real-time. The proposed emulated digital implementation of the two-channel retina model is discussed in three different points of view: processing speed, number of physical cells and accuracy. A real-time test environment with camera input and display output is going to be set up to analyze the retina model implementation on emulated digital CNN model by using a 6M gate equivalent FPGA (Field Programmable Gate Array).