Zs. J. Horváth

Evaluation of the interface state energy distribution from Schottky I‐V characteristics

The effect of the presence of an interfacial layer and interface states on the I‐V characteristics of Schottky contacts is analyzed. A simple evaluation of the interface state energy distribution and the interfacial layer thickness to its relative dielectric constant ratio (relative interfacial layer thickness) is presented for two different models concerning the quasi‐Fermi level position in Schottky contacts. The first experimental results evaluated from the I‐V characteristics of n‐type (100) GaAs‐Cr/Au mesa Schottky contacts, are in agreement with those published earlier.

Domination of the thermionic‐field emission in the reverse I‐V characteristics of n‐type GaAs Schottky contacts

The reverse I‐V characteristics of GaAs‐Cr/Au planar and mesa Schottky devices have been investigated as a function of the free electron concentration in the range of 3×1014–3×1017 cm−3. It has been obtained that the reverse characteristics have a linear region. The slope of these linear regions is higher for the planar structures than for the mesa ones. The ratio of the slopes for the planar and mesa structures with the same concentration is in agreement with the ratio of the breakdown voltages obtained on the same devices, and both of them correlate with the − 1/4 power of the concentration. The reverse characteristics calculated for the thermionic‐field (TF) emission, taking into account the image force lowering and the slopes of the linear regions, are in very good agreement with the experimental results obtained on the mesa structures. The results indicate the domination of the TF emission in the reverse characteristics of the examined devices with concentration above 8×1014 cm−3 for a large voltage ...

Investigation of electrical properties of Au porous Si Si structures

Results of capacitance-voltage (C-V) and capacitance-time measurements performed on Au/porous silicon (PS)/Si diodes having different porosity and morphology of the obtained porous layer are presented. The C-V characteristics of the studied Au/PS/Si diodes are similar to those of poor metal-insulator-semiconductor capacitors. The porosity dependence of the «insulator» capacitance is interpreted by a model assuming two parallel phases. The results obtained indicate that the C-V measurements may be useful for checking (i) the long-term stability of the metal/PS/Si junctions, (ii) the lateral homogeneity of the wafers, and (iii) the thickness and porosity of the porous layer

Comment on ‘‘Engineered Schottky barrier diodes for the modification and control of Schottky barrier heights’’ [J. Appl. Phys. 61, 5159 (1987)]

Eglash and co‐workers [J. Appl. Phys. 61, 5159 (1987)] studying the dependence of the voltage intercept of the C−2‐V plots for the engineered Schottky barrier diodes on the thickness of the p+ region used an analytical expression of the C‐V characteristics for the prediction of the voltage intercept. In this communication, a general expression is derived for the C‐V characteristics of the Schottky contacts with changing dopant concentration at the M‐S interface. It is shown that the expression used by Eglash and co‐workers is a special case of this general expression.

Two‐phase structure of plasma‐polymerized thiophene‐passivated GaAs Schottky‐like metal‐insulator‐semiconductor diodes

Recently GaAs metal‐semiconductor Schottky and plasma‐polymerized thiophene‐passivated metal‐insulator‐semiconductor (MIS) diodes were studied. The capacitance‐voltage (C‐V) results were evaluated by a simple mechanical application of the Schottky capacitance theory to the MIS devices. In this communication it is shown that there is a large discrepancy between the experimental C‐V characteristics obtained for the MIS diodes and the theoretical ones following from the depletion layer capacitance theory. The only reasonable explanation of this discrepancy is a two‐phase structure of the MIS devices, where one phase has a low‐ and the other has a high‐voltage intercept of the C−2‐V plot.

The effect of ion beam treatment and subsequent annealing on Au/GaAs contacts

The effect of Xe++ and Ar+ ion beam treatment and subsequent annealing on the Au (55 nm)/n‐GaAs system was studied using cross‐sectional transmission electron microscopy. The maximum depth of observed defects caused by Xe++ ions (700 keV, 1×1014 ions/cm2) was about 400 nm from the interface in excellent agreement with the results of capacitance‐voltage measurements. The formation of about 50‐nm‐thick polycrystalline region of GaAs was observed. The ion beam treatment resulted in the formation of defects (stacking faults, twins) down to a depth of 200 nm measured from the interface. Between 200 and 400 nm depth dislocation loops were formed. Amorphization has not been observed. The sharp Au/GaAs interface has been only slightly destroyed in the as‐implanted sample. In contrast to pits in unirradiated samples, large flat grains of Au(Ga) solid solution grown into the highly damaged region of GaAs were found in the samples annealed at 450u2009°C after the ion beam treatment. The formation of a regrown GaAs cover...

Simulation of charging properties of MNOS structures with embedded semiconductor nanocrystals

The effect of the oxide thickness and the depth, size and location of semiconductor nanocrystals are studied on the charging behaviour of MNOS non-volatile memory structures by the calculation of electron and hole tunneling probability to the nanocrystals or to the nitride conduction or valence band, respectively, and by the simulation of memory hysteresis behaviour. It is concluded for both MNOS structures that the optimal for charging behaviour tunnel oxide thickness is about 2 nm The presence of nanocrystals enhances the charge injection resulting in better performance, but for structures with thin tunnel oxide layer (below 3 nm) only, and if the nanocrystals are located close to the oxide/nitride interface. But in the case of very high tunneling probability, i.e., of high tunneling currents the system approaches eqilibrium and the memory behaviour collapses.

Investigation of electrical properties of structures

Results of capacitance-voltage (C-V) and capacitance-time measurements performed on Au/porous silicon (PS)/Si diodes having different porosity and morphology of the obtained porous layer are presented. The C-V characteristics of the studied Au/PS/Si diodes are similar to those of poor metal-insulator-semiconductor capacitors. The porosity dependence of the «insulator» capacitance is interpreted by a model assuming two parallel phases. The results obtained indicate that the C-V measurements may be useful for checking (i) the long-term stability of the metal/PS/Si junctions, (ii) the lateral homogeneity of the wafers, and (iii) the thickness and porosity of the porous layer