Zsolt József Horváth

Nanocrystal Non-Volatile Memory Devices

The physical background and present status of the application of metal-insulator-silicon structures with semiconductor nanocrystals embedded in the insulator layer for memory purposes is breafly summarized.

Si 3 N 4 based non-volatile memory structures with embedded Si and Ge nanocrystals

Memory structures with an embedded sheet of separated Si nanocrystals were prepared by low pressure chemical vapour deposition using a Si3N4 control and SiO2 tunnel layers. It was obtained that a properly located layer of Si or Ge nanocrystals can improve both the charging and rettntion behaviour of the MNOS structures simultaneously. Memory window width of about 6.6 V and retention time of 41 years has been achieved for charging pulses of ±15 V, 10 m.s.

Electrical and optical properties of InGaAsSb/GaSb

InGaAsSb layers were grown on GaSb substrates by liquid phase epitaxy. The variation of the bandgap with composition was determined and a new value for the bandgap bowing parameter is proposed. Mechanisms of the current conduction process in Au/InGaAsSb Schottky barrier structures were determined as well as the value of the Schottky barrier heights.

New trends in non-volatile semiconductor memories

The construction and the physical background of operation of floating gate, nanocrystal, silicon nitride-based, phase-change, ferroelectric and magnetoresistive memories are breafly summarized.

Current instabilities in GaAs/InAs quantum dot structures

Unexpected excess current was obtained in GaAs/InAs quantum dot structures at low temperatures and low current levels. This excess current exhibited instabilities with changing the bias, and over the time. It has been concluded that the excess current is a minority injection current connected with the high recombination rate through quantum dots. The instabilities are connected with unstable charge occupation of quantum dots.

Electrical and photoelectrical behavior of Au/n-CdTe junctions

The electrical and photo electrical behavior of Au/n-CdTe junctions prepared no CdTe mono crystalline substrates were studied. Both properties depended strongly on the parameters of the compensated high-resistive layer at the CdTe surface formed by annealing in air during preparation.