A. B. Premkumar

Design and performance analysis of a signal detector based on suprathreshold stochastic resonance

This paper presents the design and performance analysis of a detector based on suprathreshold stochastic resonance (SSR) for the detection of deterministic signals in heavy-tailed non-Gaussian noise. The detector consists of a matched filter preceded by an SSR system which acts as a preprocessor. The SSR system is composed of an array of 2-level quantizers with independent and identically distributed (i.i.d) noise added to the input of each quantizer. The standard deviation @s of quantizer noise is chosen to maximize the detection probability for a given false alarm probability. In the case of a weak signal, the optimum @s also minimizes the mean-square difference between the output of the quantizer array and the output of the nonlinear transformation of the locally optimum detector. The optimum @s depends only on the probability density functions (pdfs) of input noise and quantizer noise for weak signals, and also on the signal amplitude and the false alarm probability for non-weak signals. Improvement in detector performance stems primarily from quantization and to a lesser extent from the optimization of quantizer noise. For most input noise pdfs, the performance of the SSR detector is very close to that of the optimum detector.

A New RNS based DA Approach for Inner Product Computation

This paper presents a novel method to perform inner product computation based on the distributed arithmetic principles. The input data are represented in the residue domain and are encoded using the thermometer code format while the output data are encoded in the one-hot code format. Compared to the conventional distributed arithmetic based system using binary coded format to represent the residues, the proposed system using the thermometer code encoded residues provides a simple means to perform the modular inner products computation due to the absence of the 2 modulo operation encountered in conventional binary code encoded system. In addition, the modulo adder used in the proposed system can be implemented using simple shifter based circuit utilizing one-hot code format. As there is no carry propagation involved in the addition using one-hot code, while the modulo operation can be performed automatically during the addition process, the operating speed of the one-hot code based modulo adder is much superior compared to the conventional binary code based modulo adder. As inner product is used extensively in FIR filter design, SPICE simulation results for an FIR filter implemented using the proposed system is also presented to demonstrate the validity of the proposed scheme.

Improved memoryless RNS forward converter based on the periodicity of residues

The residue number system (RNS) is suitable for DSP architectures because of its ability to perform fast carry-free arithmetic. However, this advantage is over-shadowed by the complexity involved in the conversion of numbers between binary and RNS representations. Although the reverse conversion (RNS to binary) is more complex, the forward transformation is not simple either. Most forward converters make use of look-up tables (memory). Recently, a memoryless forward converter architecture for arbitrary moduli sets was proposed by Premkumar in 2002. In this paper, we present an extension to that architecture which results in 44% less hardware for parallel conversion and achieves 43% improvement in speed for serial conversions. It makes use of the periodicity properties of residues obtained using modular exponentiation.

A reconfigurable multi-standard channelizer using QMF trees for software radio receivers

The flexibility of a software-defined radio (SRR) depends on its capability to operate in multi-standard wireless communication environments. The most computationally intensive part of wideband receivers is the channelizer, which extracts multiple narrowband signals from adjacent frequency hands. In an SDR receiver, the compatibility of the channelizer with different communication standards is guaranteed by its reconfigurability. This paper presents an efficient channelizer that has a reconfigurable architecture based on quadrature mirror filter bank (QMF) trees. We show that the channelizer can he efficiently implemented using common subexpression based filter structures. An example of dual-mode global system for mobile communication (GSM)/personal digital cellular (PDC) channelizer is discussed to illustrate the proposed design methodology.

Error Detection and Correction in Communication Channels Using Inverse Gray RSNS Codes

A novel number theoretic transform called Inverse Gray Robust Symmetrical Number System (IGRSNS) is proposed for error control coding in this paper. IGRSNS is obtained by modifying Robust Symmetrical Number System (RSNS) that was proposed earlier, using Inverse Gray code property. Due to ambiguities present in each residue, RSNS has a short dynamic range (DR) compared to that in other number systems. The short DR of RSNS enables it to be effectively used for error detection without the addition of any redundant modulus as in Redundant Residue Number System. Although RSNS has a large redundant range, its detection ability is not optimal due to the Gray code property associated with it. In an attempt to overcome this limitation, we have proposed Inverse Gray coding to be combined with RSNS in increasing its effectiveness in error detection. The resulting IGRSNS thus inherits properties of both RSNS and Gray code. Analysis and simulations show that IGRSNS has a near-optimal error detection ability. The potential of IGRSNS for error correction is also investigated. Further, a novel error correction algorithm using one redundant modulus is proposed. Simulations show that the proposed algorithm performs well under all cases of single bit errors.

An optimal entropy coding scheme for efficient implementation of pulse shaping FIR filters in digital receivers

The most computationally intensive part of wide-band receivers is the IF processing block. Digital filtering is the main task in IF processing. Infinite precision filters require complicated digital circuits due to coefficient multiplication. This paper presents an efficient method to implement pulse shaping filters for a dual-mode GSM/W-CDMA receiver. We use an arithmetic scheme, known as pseudo floating-point (PFP) representation to encode the filter coefficients. By employing a span reduction technique, we show that the filters can be coded using an optimal entropy scheme employing PFP which requires only considerably fewer bits than conventional 24-bit and 16-bit fixed-point filters. Simulation results show that the magnitude responses of the filters coded in PFP meet the attenuation requirements of GSM/W-CDMA specifications.

Reduced complexity analogue-to-residue conversion employing folding number system

Digital signal processing (DSP) algorithms are computationally intensive and require recursive multiplication and addition. Residue number systems (RNS) offer significant advantages over conventional number systems when used in the design of special purpose DSP architectures. However, conversion of analogue signals into their residue equivalents requires first converting the signal to binary equivalents and subsequently using modular circuits to convert the resultant binary to residues. A new number system called the folding number system (FNS) is proposed and used as the basis for residue conversion. Since FNS has one-to-one correspondence with RNS, the proposed method converts the analogue signal to its RNS equivalents using concealed symmetrical residues in FNS domain. The conversion is simple and uses analogue folding circuits, comparators and combinatorial logic circuits. High-frequency analogue signals can be efficiently converted thus enabling RNS to be implemented in high-speed signal processing architectures.

Efficient Sample Rate Conversion in Software Radio Employing Folding Number System

In an ideal Software Radio, digitization of the received signal occurs immediately after receive antenna to enable channelization to be performed in the discrete time domain. However, this vision is still far from reality due to limitations of current analog to digital converter performance. In this paper, a novel number system called the Folding Number System (FNS) is proposed for use in Software Radio. We implement sample rate conversion immediately after the receive antenna using this number system thus providing an efficient solution to the above problem. By decomposing the input analog signal into separate channels in parallel, symmetrical residues are obtained with reduced number of comparators. These residues together with the folding information are processed in parallel in the FNS domain. The FNS has the same computational complexity as that in Residue Number System but the need for the intermediate steps such conversion of the analog data into binary and subsequently into residues is absent.

Narrowband signal detection techniques in shallow ocean by acoustic vector sensor array

This paper presents the formulation and performance analysis of four techniques for detection of a narrowband acoustic source in a shallow range-independent ocean using an acoustic vector sensor (AVS) array. The array signal vector is not known due to the unknown location of the source. Hence all detectors are based on a generalized likelihood ratio test (GLRT) which involves estimation of the array signal vector. One non-parametric and three parametric (model-based) signal estimators are presented. It is shown that there is a strong correlation between the detector performance and the mean-square signal estimation error. Theoretical expressions for probability of false alarm and probability of detection are derived for all the detectors, and the theoretical predictions are compared with simulation results. It is shown that the detection performance of an AVS array with a certain number of sensors is equal to or slightly better than that of a conventional acoustic pressure sensor array with thrice as many sensors.

RNS encoding based folding ADC

This paper presents a novel encoding scheme based on the residue number systems for folding ADC to enable highly efficient hardware implementation of high speed, high resolution ADC. The input analog signal is folded by multiple groups of zero-crossing based folding circuits of different folding factors corresponding to the moduli used for their implementation. Each group of folding circuits in turn contains multiple parallel zero-crossing based folding circuits of same folding factor, but with their outputs phase shifted with respect to one another such that their collective output bits pattern form a residue of the modulus of the group. Multiple groups of folding circuits with different moduli that are relatively prime to each other are then combined in parallel. When taken together, their digital outputs form residue digits of a relatively prime moduli set that allows unique representation of the input signal magnitude over a dynamic range that is equal to the product of the moduli used in the different groups in the ADC.