E.M.-K. Lai

On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods

The most computationally intensive part of a wideband receiver is the channelizer. The computational complexity of linear phase finite impulse response (LPFIR) filters employed in the channelizer is dominated by the number of adders used in the implementation of the multipliers. In this paper, two methods are proposed to efficiently implement the channel filters in a wideband receiver based on common subexpression elimination (CSE). We exploit the fact that a significant amount of redundant multiplications exist in the filter-bank channelizer as it extracts multiple narrowband channels from the wideband signal. By forming three and four nonzero-bit super-subexpressions utilizing redundant identical shifts that exist between a two- nonzero-bit common subexpression (CS) and a third nonzero bit, or between two nonzero-bit CS, the number of adders to implement the channel filters can be reduced considerably. Furthermore, the complexity of the adders is analyzed and design examples of the channel filters employed in the digital advanced mobile phone system (D-AMPS) and the personal digital cellular (PDC) channelizers show that the proposed methods offer considerable reduction in the number of full adders when compared to conventional CSE methods.

Improved memoryless RNS forward converter based on the periodicity of residues

The residue number system (RNS) is suitable for DSP architectures because of its ability to perform fast carry-free arithmetic. However, this advantage is over-shadowed by the complexity involved in the conversion of numbers between binary and RNS representations. Although the reverse conversion (RNS to binary) is more complex, the forward transformation is not simple either. Most forward converters make use of look-up tables (memory). Recently, a memoryless forward converter architecture for arbitrary moduli sets was proposed by Premkumar in 2002. In this paper, we present an extension to that architecture which results in 44% less hardware for parallel conversion and achieves 43% improvement in speed for serial conversions. It makes use of the periodicity properties of residues obtained using modular exponentiation.

An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters

Algorithms that minimize the complexity of multiplication in digital filters focus on reducing the number of adders needed to implement the coefficient multipliers. Previous works have not analyzed the complexity of each adder, which is significant in low-complexity implementation. A multiplication algorithm for low-complexity implementation of digital filters with a minimum number of full adders (NFAs) and improved speed is proposed here. The authors exploit the fact that when multiplication is implemented using shifts and adds, the adder width can be minimized by limiting the shifts of the operands to shorter lengths. The coefficient-partitioning (CP) algorithm proposed here minimizes the shifts of the operands of the adders by partitioning each coefficient into two subcomponents. The authors show that by combining three methods, the CP algorithm, an efficient coefficient coding scheme known as pseudo floating-point (PFP) representation, and the well-known common subexpression elimination (CSE), the NFAs required in each adder of the multiplier can be reduced considerably. Design examples show that the method offers an average FA reduction of 30% for finite-impulse response (FIR) filters and 20% for infinite-impulse response (IIR) filters over CSE methods.

A reconfigurable multi-standard channelizer using QMF trees for software radio receivers

The flexibility of a software-defined radio (SRR) depends on its capability to operate in multi-standard wireless communication environments. The most computationally intensive part of wideband receivers is the channelizer, which extracts multiple narrowband signals from adjacent frequency hands. In an SDR receiver, the compatibility of the channelizer with different communication standards is guaranteed by its reconfigurability. This paper presents an efficient channelizer that has a reconfigurable architecture based on quadrature mirror filter bank (QMF) trees. We show that the channelizer can he efficiently implemented using common subexpression based filter structures. An example of dual-mode global system for mobile communication (GSM)/personal digital cellular (PDC) channelizer is discussed to illustrate the proposed design methodology.

Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filters

Common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the coefficient multipliers in digital filters. Two classes of common subexpressions (CS) occur in the canonic signed digit (CSD) representation of coefficients, called the horizontal and the vertical CS. Previous works have not addressed the trade-offs in using these two types of CS on the delay and the number of multiplier block adders. We provide a comparison of hardware reductions achieved using the horizontal and the vertical CS in realizing digital filters. We show that the CSE technique employing horizontal CS offers better reductions in the number of adders and critical paths than its vertical CS counterpart in practical linear phase finite impulse response (LPFIR) filter implementations. Our simulation results show that the hardware reductions offered by the vertical CS in implementing infinite impulse response (IIR) filters are improved compared to their LPFIR counterparts.

An optimal entropy coding scheme for efficient implementation of pulse shaping FIR filters in digital receivers

The most computationally intensive part of wide-band receivers is the IF processing block. Digital filtering is the main task in IF processing. Infinite precision filters require complicated digital circuits due to coefficient multiplication. This paper presents an efficient method to implement pulse shaping filters for a dual-mode GSM/W-CDMA receiver. We use an arithmetic scheme, known as pseudo floating-point (PFP) representation to encode the filter coefficients. By employing a span reduction technique, we show that the filters can be coded using an optimal entropy scheme employing PFP which requires only considerably fewer bits than conventional 24-bit and 16-bit fixed-point filters. Simulation results show that the magnitude responses of the filters coded in PFP meet the attenuation requirements of GSM/W-CDMA specifications.

Optimizing vertical common subexpression elimination using coefficient partitioning for designing low complexity software radio channelizers

The complexity of finite impulse response (FIR) filters used in the channelizer of a software defined radio (SDR) receiver is dominated by the complexity of the coefficient multipliers. A method for designing low complexity channel filters by optimizing vertical common subexpression elimination (VCSE) using coefficient partitioning is presented. Our algorithm exploits the fact that when multiplication is implemented using shifts and adds, the adder width can be minimized by limiting the shifts of the operands to shorter lengths. Design examples of the channel filters employed in the digital advanced mobile phone system (D-AMPS) receiver show that the proposed method offers considerable full adder reduction over VCSE methods.

Minimizing embedded software power consumption through reduction of data memory access

Software applications that involve multimedia signal processing typically have to process large amounts of data. They often involve the handling of data arrays in the form of nested loops. Experiments show that for this kind of applications data transfer (memory access) operations consume much more power than data-path operations. Our objective is to reduce memory access related power consumption by reducing the number of data transfers between processor and memory, or between a higher (closer to processor) level of memory and a memory at a lower level using source program transformation. The procedure involves profiling, inlining and globed transformation. The effectiveness of this procedure is illustrated by applying it to the software for a wideband adaptive multi-rate (WB-AMR) speech decoder which can be obtained from the official website of the 3rd Generation Partnership Project (3GPP).

Design of low complexity high-speed pulse-shaping IIR filters for mobile communication receivers

Low-complexity and high-speed design of infinite impulse response (IIR) filters focuses on minimizing the number of logic operators and the logic depth in the implementation of the coefficient multipliers. Although the Bull-Horrocks modified (BHM) and the n-dimensional reduced adder graph (RAGn) algorithms result in considerable reduction of logic operators (LO), it uses the highest logic depth (LD) and hence the resulting IIR filters are not optimized in view of filtering speed. The Hartley algorithm proposed for finite impulse response (FIR) filters offers a reduction in LD, but it requires additional LO respect to BHM technique. A method to minimize the number of LO and the LD in the multipliers of pulse-shaping IIR filters by efficiently combining Hartleys horizontal common subexpressions and vertical common subexpressions that occur across the filter coefficients is proposed here. Design examples of pulse-shaping filters employed in a dual-mode GSM/W-CDMA receiver show that our method offers reduction of complexity as well as delay when compared with earlier methods.

Low-complexity filter bank channelizer for wideband receivers using minimum adder multiplier blocks

The computational complexity of linear phase finite impulse response (LPFIR) filters used in the channelizer of a wideband receiver is dominated by the number of adders (subtracters) employed in the multipliers. Common subexpression elimination (CSE) is a well-known technique for minimizing the number of adders in LPFIR filters. An improved CSE method is proposed in this paper, which is used to implement the channel filters of a filter bank channelizer (FBC). In the FBC, each modulated bandpass filter extract one channel from the input wideband signal. The reduction in number of adders is obtained by eliminating redundant multiplications of common subexpressions that exist among the channel filters of the FBC with the input signal. Design example of the channel filters employed in the digital advanced mobile phone system (D-AMPS) show that the proposed method offers considerable reduction in the number of full adders when compared with conventional CSE methods.