A. Ben Atitallah

Hardware architecture for H.264/AVC deblocking filter algorithm

This paper presents novel hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264/AVC baseline profile video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. We use a novel edge filter ordering in a Macroblock to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 150 MHz in an ALTERA Stratix II FPGA.

HW/SW FPGA Architecture for a Flexible Motion Estimation

In this paper, we present a HW/SW implementation of the motion estimation on a FPGA circuit using the Nios II softcore processor. Furthermore, in multimedia processing, it is well-known that the sum of absolute differences (SAD) operation is the most time consuming operation when it is implemented in a software approach. Our implementation takes into account more than one algorithm of motion estimation processing and supports a parallel hardware implementation of the SAD operation. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S60 FPGA circuit. The performances of our design have been tested using the H.263 video encoder.

An efficient pipeline execution of H.264/AVC intra 4×4 frame design

In this paper, we present an implementation of an optimized H.264 intra 4×4 algorithm in order to reduce the time of the intra 4×4 process. However the source of waste time in conventional architecture of intra 4×4 is the serialization of intra prediction and reconstruction of sixteen 4×4 blocks in one macroblock and the intra prediction of the current 4×4 block cannot be performed before the reconstruction of the previous 4×4 block. Therefore, for a high speed implementation we replaced the conventional one by a pipelined architecture while maintaining consistency with the standard. So we have studied ten alternative scanning orders based on rearranging order of intra 4×4 and we choose the best one which reduce dependencies between consecutively executed blocks without performance degradation. This order is implemented by a pipelined architecture using VHDL language. The VHDL code is verified to work at 100 MHz in an ALTERA Stratix II EP2S60F1020C3 FPGA. As a result, the processing time is reduced by 31.25% compared to the conventional implementation. So, it can be a good solution for real-time video application. The H.264 intra 4×4 hardware and software are demonstrated to work together on ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA.

FPGA implementation of a HW/SW platform for multimedia embedded systems

This paper presents a HW/SW platform for embedded video system. It has been designed around an embedded RISC processor and FPGA technologies and provides video input and output interfaces. The configurable platform has been used to implement a real time video processing and vision systems. The Altera’s Nios II development board was chosen to realise this real time video platform which uses μClinux as embedded Linux Operating System. Experimental results using H.263 video encoder show that this platform provides enough resources and speed to implement even complex multimedia embedded systems in real time.

Hardware platform design for real-time video applications

In this paper, we present the installation of a hardware platform for video acquisition and restitution in real-time using a mixed software/hardware environment. The hardware platform is based on the Altera STRATIX development board. Besides, it is completed with a camera interface for acquisition and a VGA interface for restitution. The core of the system incorporates an IP module (intellectual property) of Altera Nios processor in the Quartus II development tool of Altera. During this study, we have used video sequences, which are acquired, processed and visualized while respecting temporal constraints.

A parallel hardware architecture of deblocking filter in H264/AVC

This paper describes an efficient hardware architecture for the deblocking filter used in H.264/AVC baseline profile video coding standard and optimized for real time implementation. Thus, the deblocking filter is a computationally and data intensive tool resulting in an increased execution time of both encoding and decoding processes. In fact, the processing order of the filter and the memory organization are rearranged to facilitate the deblocking of the pixels in a parallel fashion and to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. The proposed architecture is implemented in synthesizable HDL at RTL level and verified with the reference software. This hardware is designed to be used as part of a complete H.264/AVC decoder.

Hardware implementation of fast block matching algorithm in FPGA for H.264/AVC

Motion estimation (ME) is one of the most time-consuming parts in video encoding system, and significantly affects the output quality of an encoded sequence. In this paper, we present hardware implementation of the Large Diamond Parallel search algorithm. This hardware is designed to be used as part of a complete H.264 video coding system. This architecture is simulated and tested using VHDL and synthesized using Altera Quartus II version 5.1. Also, This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The VHDL code is verified to work at 100 MHz in ALTERA Stratix II FPGA.

Performances analysis and evaluation of Xenomai with a H.264/AVC decoder

The expansion of the market for embedded systems has motivated academic research to offer solutions to the problems of congestion and connectivity. Indeed, the implementation of the embedded processor on FPGA helps saving space and provides a better interaction between the program and hardware acceleration. Furthermore, the addition of an Operating System (OS) allows to abstract the hardware and to control devices by software. In fact, all these parameters converge to use a Real-Time Operating System implemented in FPGA (in our case, FPGA Xilinx Virtex 5 ML507 board is used). The basic idea of this paper is to evaluate the performances of Xenomai running in the PowerPC processor, with the H.264/AVC video decoder.

An FPGA implementation of motion estimation algorithm for H.264/AVC

The H.264/AVC standard achieves much higher coding efficiency than previous video coding standards. Unfortunately mis comes with a cost in considerably increased complexity at the encoder mainly due to motion estimation. Therefore, various fast algorithms have been proposed for reducing computation but they do not consider how they can be effectively implemented by hardware. In this paper, we propose a hardware architecture of fast search block matching motion estimation algorithm using Line Diamond Parallel Search (LDPS) for H.264/AVC video coding system. This architecture presents pipeline processing techniques, minimum latency, maximum throughput and full utilization of hardware resources. The VHDL code has been tested and can work at high frequency in a Xilinx Virtex-5 FPGA circuit.

An efficient hardware architecture design for H.264/AVC INTRA 4×4 algorithm

In this work, we present architecture for real-time implementation of INTRA 4X4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4times4 is composed by intra prediction 4times4, integer transform 4times4, quantization 4times4, inverse integer transform 4times4, inverse quantization 4times4. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 160 MHz in an ALTERA Stratix II FPGA. This architecture can process one macroblock (MB) for 432 clock cycles.