Perceval Coudrain

Advances, challenges and opportunities in 3D CMOS sequential integration

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.

3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS

3-D sequential integration stands out from other 3-D schemes as it enables the full use of the third dimension. Indeed, in this approach, 3-D contact density matches with the transistor scale. In this paper, we report on the main advances enabling the demonstration of functional and performant stacked CMOS-FETs; i.e., wafer bonding, low temperature processes (<;650°C) and salicide stabilization achievements. This integration scheme enables fine grain partitioning and thus a gain in performance versus cost ratio linked to separation of heterogeneous technologies on distinct levels. In this work, we will detail examples taking advantage of the unique 3-D contact pitch achieved with sequential 3-D.

Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors

This paper presents an innovative 3D architecture capable of overcoming pixel miniaturization drawbacks. Back-illuminated photodiodes are realized on a first silicon layer, while readout transistors are located on a second silicon layer. Implications of a sequential integration are evaluated in the perspective of low noise pixel performances with a comprehensive study on: 1/ setting the thermal budget limit to 700degC to preserve transfer gate performances, 2/ transferring high quality SOI by direct bonding 3/ processing HfO2/TiN fully depleted transistors, exhibiting noise levels close to standard 2.2 mum pixels, with improvement solutions.

Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.

Electrical and morphological assessment of via middle and backside process technology for 3D integration

This study focuses on the prototype of a 3D circuit in 65nm CMOS node, in which digital and analog functions have been partitioned on two different layers, assembled in a face-to-face integration and reported on a BGA. The paper more specifically presents the process technology carried out for the realization of the bottom die. Major process steps are described and evaluated from an electrical performance point of view.

Thermal performance of 3D ICs: Analysis and alternatives

3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphite-based heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45μC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.

Investigation of a Sequential Three-Dimensional Process for Back-Illuminated CMOS Image Sensors With Miniaturized Pixels

A new 3-D CMOS image sensor architecture is presented as a potential candidate for submicrometer pixels. To overcome the scaling challenge related to miniaturized pixel design rules, far beyond traditional 3-D stacking alignment capabilities, a sequential construction is applied. This paper gives a technical overview of this 3-D scheme and validates a part of its building blocks. As a consequence of a sequential process, the thermal budget is limited to ensure bottom device immunity. Subsequently, high-quality SOI film transfer above the first layer by direct bonding and etch back is demonstrated. Finally, the low-temperature processing of HfO2/TiN fully depleted silicon-on-insulator readout transistors is detailed and evaluated from a low frequency noise point of view.

Using TSVs for thermal mitigation in 3D circuits: Wish and truth

3D technology is envisioned to offer advanced integration capabilities, enabling heterogeneous system integration and offering improved performance and reduced power consumption thanks the so-called Through Silicon Vias (TSVs). Nevertheless, 3D integration is facing strong thermal issues due to its higher power density and reduced heat dissipation properties. In previous studies, it has been often reported the use of TSV insertion techniques for thermal mitigation in 3D stacked circuits. However, due to the thin oxide layer isolating TSVs from silicon substrate, the expected thermal mitigation is actually not effective for the current TSV technologies. This paper firstly provides an analytical study to project the potential benefits and drawbacks of using TSVs for thermal mitigation. Detailed FEM simulations and experimental silicon data from a dedicated thermal test chip are then used to confirm the projections and demonstrate that TSVs may even increase the temperature of hotspots. This paper secondly reports the study of the thermal performance of multiple TSV arrays using thermal simulations for various system-level configurations, including a WideIO compatible 3D circuit. Similar results are obtained where, besides not alleviating thermal issues, TSVs may produce exacerbated hotspots. The results presented in this paper indicate that the use of additional area costly TSVs for thermal mitigation is not worthy.

3D integration demonstration of a wireless product with design partitioning

3D integration has now made a place in semiconductor landscape and is coming closer from implementation in manufacturing. Although process bricks are almost all available now, there are still several challenges to solve before it is introduced in standard flows. One of those which is not commonly addressed is to get final customers interest by showing him evaluations and results on real industrial applications. Heterogeneous integration and the possibility to partition different functions of a product in separate layers is one of the advantages of 3D integration. In this paper, product partitioning with TSV and 3D integration is demonstrated without inducing any impact on final product functionality and on early package level reliability tests.

Advances toward reliable high density Cu-Cu interconnects by Cu-SiO 2 direct hybrid bonding

Cu-SiO2 direct hybrid bonding is considered as one of the most promising approaches for matching the needs of three dimensional integrated circuits (3D-IC). In this paper we present the results of a complete morphological, electrical and reliability study conducted on four-layer copper structures realized by Cu-SiO2 direct hybrid bonding. Ultra-fine 7 μm pitch, 3 μm × 3 μm pads daisy chains with up to 30 160 connections are bonded with submicron accuracy, matching the interconnection needs in upcoming 3D circuits. A focus is paid on the influence of the temperature of annealing on the bonding quality and electrical performances. Thanks to SEM, FIB/SEM tomography, AFM, TEM and TEM-EDX analysis, the morphology of the bonded structures is described. Electrical parametric tests exhibit very low resistance structures, with high functional yields and low variability. State-of-the-art contact resistivity is obtained for 200 and 400 °C treatments. Unbiased HAST, temperature cycling and temperature storage tests demonstrate excellent reliability performances. Finally, an electromigration resistance comparative study is conducted on bonded copper lines with TaN/Ta and TiN diffusion barriers.