A.G. Martinez-Lopez

Parasitic Gate Capacitance Model for Triple-Gate FinFETs

Triple-gate FinFETs have demonstrated to be promising candidates to push further the performance limits of the microelectronics industry, thanks to their high immunity to short-channel effects. However, owing to their 3-D nature, high parasitic gate capacitances appear that dramatically degrade their high-speed digital and analog/RF performances. Thus, in order to meet the International Technology Roadmap of Semiconductors projection, it is mandatory to find layout or technological solutions to reduce the total parasitic gate capacitance. In this context, it is necessary to develop a model that describes the parasitic capacitance in terms of the FinFET geometry. In this paper, a semianalytical extrinsic gate capacitance model for silicon-on-insulator triple-gate FinFET, based on 3-D numerical simulations, is presented. The model takes into account the external (five components) and internal (two components) fringing capacitances from the gate to the source/drain electrodes as well as the overlap capacitances. Comparisons with experimental results are presented to validate the developed model. Finally, based on the developed model, the evolution of the total parasitic gate capacitance as the channel length is reduced toward the 12-nm technology node is analyzed.

2-bit

The design and performance of a 2-bit p-i-n diode reflective X-band phase shifter are described. This phase shifter uses the spiraphase principle of phase changing. Benzocyclobutene-based bias circuits are used to decrease the insertion loss level and to reduce the fabrication costs. It has been proven that the phase shifter demonstrates insertion loss better than 0.5 dB in the frequency band from 9.75 to 11.5 GHz for all four phase states. The phase shifter is characterized by maximum phase errors of 11deg in the frequency band from 9.75 to 11.25 GHz. The measured switching time of the phase shifter is less than 150 ns

X

In this paper, we develop an analytical model to simulate strained silicon NMOSFETs, which allows to describe the drain current. Numerical simulations were performed in order to validate the model, where different technological parameters were considered (e.g. impurity concentrations in Si1-yGey and strained-silicon films). A good agreement with numerical simulations has been obtained.

-Band Reflective Waveguide Phase Shifter With BCB-Based Bias Circuits

The microelectronics industry has progressed astonishingly along several decades, thanks to the MOS transistor shrinkage. However, the parasitic gate capacitance becomes an important concern for device behavior optimization in the nanometric range. The fringing parasitic gate capacitance exhibits weaker channel length dependence than the intrinsic counterpart. For this reason, the relative weight of the parasitic gate capacitance will be more significant for future technology nodes. In this contribution, an extraction procedure to determine the main fringing components of a simple MOS structure is presented. Numerical simulations were used to validate the presented methodology. Finally, results indicate that for sub-25 nm gate electrode length, normalized total fringing capacitance associated to the transistor width is greater than the intrinsic counterpart.

Drain current model for bulk strained silicon NMOSFETs

CMOS technology has been guided by the continuous reduction of MOS transistors used to fabricate integrated circuits. Additionally, the use of high-k dielectrics as well as a metal gate electrode have promoted the development of nanometric MOS transistors. Under this scenario, the proper modelling of the gate capacitance, with the aim of adequately evaluating the dielectric film thickness, becomes challenging for nanometric metal-insulator-semiconductor (MIS) structures due to the presence of extrinsic fringing capacitance components which affect the total gate capacitance. In this contribution, a complete intrinsic–extrinsic model for gate capacitance under accumulation of an MIS structure, together with an extraction procedure in order to independently determine the different capacitance components, is presented. ATLAS finite element simulation has been used to validate the proposed methodology.

Extraction procedure for MOS structure fringing gate capacitance components

In this paper, based on a full intrinsic-extrinsic model for symmetric doped double-gate MOSFET, we analyze the impact of FinFET gate resistance over the inverter and ring oscillator performance. It is shown that, when the total number of fins remains constant, the propagation delay can be improved thanks to the multifinger configuration that translates into the gate resistance reduction. Furthermore, the fin spacing in addition to source/drain fin extension reduction are of primary importance to improve the digital circuit performance.

Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure

Most of RFID tags for radiofrequency identification applications are different among them since its design and fabrication process rely on intended application environment. Thus, RFID tag antennas should be made of materials suitable for its target application scenario allowing in the end, an efficient means for identification. In this paper, design and fabrication details of flexible RFID tags antennas is discussed, those tags were attached to a chip in order to measure the working area of the tags. Three prototypes of RFID antennas working in the UHF band of the spectrum were built by integrating it in Rogers RT/Duroid 5880 substrate which is flexible, can be easily finished and resist most chemicals used for printed circuit board fabrication, that is why is widely used for making antennas.

Parasitic Gate Resistance Impact on Triple-Gate FinFET CMOS Inverter

A new extraction method of the intrinsic parameters of the small-signal equivalent circuit model of SOI MOS transistors (MOSFET) is presented. This new method does not need the previous knowledge of the extrinsic series resistances, moreover, it is possible to directly determine the intrinsic parameters at the bias point of interest. Floating-Body SOI MOSFETs are analyzed using this method.