J.C. Tinoco

Room temperature plasma oxidation mechanism to obtain ultrathin silicon oxide and titanium oxide layers

Abstract Scaling rules for sub-micrometric MOS devices have led to the necessity of ultrathin dielectric films and high- k dielectric layers. In this paper we present first results of room temperature plasma oxidation to obtain ultrathin layers of SiO 2 and TiO 2 . The oxidation process in O 2 and N 2 O shows a power law dependence with time and inverse proportionality with pressure. The oxidation rate is inversely proportional to pressure for both high and medium resistivities substrates. An oxidation model is proposed to explain this behavior. Ellipsometric and C – V characterization show complete oxidation of titanium verifying that a dielectric layer is formed.

Conduction mechanisms of silicon oxide/titanium oxide MOS stack structures

Abstract During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO2 films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason, stack structures with SiO2 as an interfacial layer between silicon substrate and high-k film have been studied. In this contribution we analyze the main conduction mechanism observed in SiO2/TiO2 MOS stack structures obtained by room temperature plasma oxidation in different conditions and reactors. Films fabricated in a parallel-plate type reactor showed better quality with low current density where thermionic conduction mechanism is predominant. In lower quality films, for example those fabricated in a barrel type equipment, the current density is higher and the conduction mechanism observed is Poole–Frenkel. Finally we show that the presence of thermionic mechanism provides a weak thickness dependence and a strong current density reduction with respect to silicon oxide MOS structures with the same equivalent oxide thickness.

Parasitic Gate Capacitance Model for Triple-Gate FinFETs

Triple-gate FinFETs have demonstrated to be promising candidates to push further the performance limits of the microelectronics industry, thanks to their high immunity to short-channel effects. However, owing to their 3-D nature, high parasitic gate capacitances appear that dramatically degrade their high-speed digital and analog/RF performances. Thus, in order to meet the International Technology Roadmap of Semiconductors projection, it is mandatory to find layout or technological solutions to reduce the total parasitic gate capacitance. In this context, it is necessary to develop a model that describes the parasitic capacitance in terms of the FinFET geometry. In this paper, a semianalytical extrinsic gate capacitance model for silicon-on-insulator triple-gate FinFET, based on 3-D numerical simulations, is presented. The model takes into account the external (five components) and internal (two components) fringing capacitances from the gate to the source/drain electrodes as well as the overlap capacitances. Comparisons with experimental results are presented to validate the developed model. Finally, based on the developed model, the evolution of the total parasitic gate capacitance as the channel length is reduced toward the 12-nm technology node is analyzed.

RF-extraction methods for MOSFET series resistances: A fair comparison

Adequate modeling of MOS transistors for RF applications requires the accurate extraction of the extrinsic series resistances. In this paper, we fairly compare several RF extraction methods based on simulation results provided by an accurate foundry compact model of advanced RF MOSFETs. We demonstrate that all published RF characterization methods properly work to extract the extrinsic series resistances when the RF measurement noise is not considered. However, when Vectorial Network Analyzer (VNA) measurement noise on S-parameters is included in the simulations, we clearly conclude that the extracted series resistances are dependent on the extraction procedure. These results demonstrate the high sensitivity of the extracted RF MOSFETs small-signal equivalent circuit with S-parameters measurement noise and therefore the need of specific filtering methods to reduce the VNA noise floor.

Revised RF Extraction Methods for Deep Submicron MOSFETs

Adequate modelling of MOS transistors for RF applications requires the accurate extraction of the extrinsic series resistances. In this paper, we fairly compare several RF extraction methods based on simulation results provided by an accurate foundry compact model of advanced RF MOSFETs. We present the relative sensitivity of each published RF characterization method to the measurement noise floor of Vectorial Network Analyzer. Additionally, the Bracales method demonstrates to be less sensitive to the measurement noise but the extracted resistance values suffer from the mobility degradation due to the transversal electric field and the asymmetry of the device under test. Based on these theoretical and experimental results we propose a revised extraction procedure suitable for deep submicron transistors.

Compact small-signal model for RF FinFETs

Modeling of the small-signal equivalent circuit of SOI FinFETs through SPICE simulations is presented. A compact model implemented in Verilog-A predicts well the DC characteristics of RF SOI FinFETs and allows the extraction of the intrinsic conductance, transconductance and capacitances at any selected operating point. The intrinsic small-signal equivalent circuit composed of those extracted lumped elements is used in SPICE simulator. This paper compares the parameters extracted from both DC and wideband S-parameter methods.

RF compact small-signal model for SOI DG-MOSFETs

A compact model for small-signal equivalent circuit of DG-MOSFETs is presented. The intrinsic parameters are obtained from DC analytic compact model. This DC model allows determining the mobile charge inside the transistor channel, from which the intrinsic parameters are derived. Additionally, the extrinsic capacitances are calculated and included into the model. This compact small-signal model allows determining the transistor RF behavior at different bias conditions and for different technological parameters in a more simple and precise way.

Drain current model for bulk strained silicon NMOSFETs

In this paper, we develop an analytical model to simulate strained silicon NMOSFETs, which allows to describe the drain current. Numerical simulations were performed in order to validate the model, where different technological parameters were considered (e.g. impurity concentrations in Si1-yGey and strained-silicon films). A good agreement with numerical simulations has been obtained.

Advanced RF MOSFET´s for Microwave and Millimeter Wave Applications: RF Characterization Issues

The communication industry has always been a very challenging and profitable market for semiconductor companies. The new communication systems are today very demanding; they require high frequency, high degree of integration, multi-standards, low power consumption, and they have to present good performance under harsh environment. The integration and power consumption reduction of the digital part will further improve with the continued downscaling of technologies. The bottleneck for further advancement is the analog front-end. Present-day transceivers often consist of a three or four chip-set solution combined with several external components. A reduction of the external components is essential to obtain a lower cost, power consumption and weight, but it will lead to a fundamental change in the design of analog front-end architectures. The analog front-end requires a high performance technology, like GaAs or silicon bipolar transistors, with devices that can easily achieve operating frequencies in the GHz range. For a digital signal processor, a small device feature size is essential for the implementation of complex algorithms. Therefore, it appears that only the best submicron CMOS technology is suitable for a feasible and cost-effective integration of the communication systems. This last decade MOS transistors have reached amazingly high operation speed and the semiconductor community has noticed the Radio Frequency possibilities of such mainstream devices. Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency reaching cutoff frequencies close to 500 GHz for nMOSFETs and for harsh environment (high temperature, radiations) commercial applications. From its early development phase till recent years, SOI has grown from a mere scientific curiosity into a mature technology. Partially Depleted (PD) SOI is now massively serving the 45-nm digital market where it is seen as a low cost low power alternative to bulk silicon. Fully depleted (FD) devices are also widely spread as they outperform existing semiconductor technologies for extremely low power analog applications. 9

Threshold voltage model for bulk strained-silicon NMOSFETs

In the last few years, different devices have been studied, motivated by the continuous development of microelectronics technology. One of them is the strained-silicon transistor, in search of enhanced carrier mobility. For this type of transistor, there are few works related to analytical models for the threshold voltage. Due to its importance, in this contribution we present an analytic model for the threshold voltage of n-type bulk strained-silicon transistors. The model is in terms of the technological parameters such as the strained-silicon film thickness, impurity and germanium concentrations in the silicon–germanium substrate. The validation of the voltage threshold model was done using 2D numerical simulations by ATLAS.