A. Cerdeira

A review of recent MOSFET threshold voltage extraction methods

The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be extracted from either measured drain current or capacitance characteristics, using a single or more transistors. Practical circuits based on some of the most common methods are available to automatically and quickly measure the threshold voltage. This article reviews and assesses several of the extraction methods currently used to determine the value of threshold voltage from the measured drain current versus gate voltage transfer characteristics. The assessment focuses specially on single-crystal bulk MOSFETs. It includes 11 different methods that use the transfer characteristics measured under linear regime operation conditions. Additionally two methods for threshold voltage extraction under saturation conditions and one specifically suitable for non-crystalline thin film MOSFETs are also included. Practical implementation of the several methods presented is illustrated and their performances are compared under the same challenging conditions: the measured characteristics of an enhancement-mode n-channel single-crystal silicon bulk MOSFET with state-of-the-art short-channel length, and an experimental n-channel a-Si:H thin film MOSFET. 2002 Elsevier Science Ltd. All rights reserved.

New procedure for the extraction of basic a-Si:H TFT model parameters in the linear and saturation regions

Abstract A new procedure is proposed to extract basic parameters for the AIM-Spice amorphous thin film transistor model in the above-threshold region. Our method avoids non-linear optimization, which is mainly the method utilized up to now, when using a program extractor included in AIM-Spice. The present extraction procedure is based on the integration of the experimental data current. The integration method as in known is convenient to decrease the effects of experimental noise. The method is applied to the linear and saturation regions for the above-threshold regime and allows the extraction of all the above-threshold parameters. The accuracy of the simulated curves using the parameters extracted with the new procedure is verified with measured and calculated data using the expressions contained in the model.

New method for determination of harmonic distortion in SOI FD transistors

We present a new method for calculating the total harmonic distortion (THID) and the third harmonic distortion (HD3) of the output current-voltage characteristics of a semiconductor device. The method is based on the calculation of two functions which we call D and D3 and are based on a specific integration of the DC current-voltage characteristic of the device. In this paper we demonstrate that function D can be correlated with the THD and function D3 with the HD3, so that they can be determined in a much simpler way, with no need to use derivatives, Fourier coefficients or fast Fourier transforms. The new method is applied to calculate the harmonic distortion of a silicon-on-insulator (Sol) fully depleted (FD) MOS transistor in the triode regime to be used as an active resistor at the input of an operational amplifier in a MOSFET-C filter configuration. It is also demonstrated that the transistor I-DS-V-DS characteristics used in these calculations can be obtained from either measurements, analytical models or numerical simulations

Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor

In this paper, we analyze the previously unexpected advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The study of the two major figures of merit in such applications as on-resistance and nonlinear harmonic distortion, is supported by both measurements and simulations of conventional and graded-channel (GC) fully depleted silicon-on-insulator (SOI) MOSFETs. The quasi-linear current-voltage characteristics of GC transistors show a decrease of the on-resistance as the length of the low doped region in the channel is increased, as well as an improvement in the third-order harmonic distortion (HD3), when compared with conventional transistors. A method for full comparison between conventional and GC SOI MOSFETs is presented, considering HD3 evolution with on-resistance tuning under low voltage of operation. Results demonstrate the significant advantages provided by the asymmetrical long channel transistors.

New procedure for the extraction of a-Si:H TFTs model parameters in the subthreshold region

Abstract In a previous paper we presented a new procedure to extract basic AIM-Spice model parameters of amorphous thin film transistor model in the above-threshold region, based on the integration of the experimental data current. In this paper we present a new procedure to determine subthreshold TFT parameters highly dependent on the fabrication technology as the density of deep states and characteristic temperature of deep states. These parameters are extracted in a simple and direct way from the experimental measurements, with no need of assigning predetermined values to any other model parameter. Other parameters required for device modeling in the subthreshold regime are also determined. The validity of the procedure is tested for a-Si:H TFTs with channel length down to 4 μm. We also show the good coincidence between calculated, using parameter values obtained with our new extraction procedure and experimental curves, in all working regions of the devices. Finally we discuss effects in the behavior of IDS vs. VDS curve related to the series resistance at the drain and source, which become evident during the device modeling.

Conduction mechanisms of silicon oxide/titanium oxide MOS stack structures

Abstract During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO2 films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason, stack structures with SiO2 as an interfacial layer between silicon substrate and high-k film have been studied. In this contribution we analyze the main conduction mechanism observed in SiO2/TiO2 MOS stack structures obtained by room temperature plasma oxidation in different conditions and reactors. Films fabricated in a parallel-plate type reactor showed better quality with low current density where thermionic conduction mechanism is predominant. In lower quality films, for example those fabricated in a barrel type equipment, the current density is higher and the conduction mechanism observed is Poole–Frenkel. Finally we show that the presence of thermionic mechanism provides a weak thickness dependence and a strong current density reduction with respect to silicon oxide MOS structures with the same equivalent oxide thickness.

Extraction method for polycrystalline TFT above and below threshold model parameters

A procedure is presented to extract above and sub-threshold model parameters in polysilicon TFTs. It is based on the integration of the experimental data current, which has the advantage of reducing the effects of experimental noise. This method is applied to the linear and saturation regions for the above-threshold regime and allows the extraction of all the above-threshold and sub-threshold parameters. We already presented a unified extraction method for the above threshold parameters of a-Si:H and polysilicon TFTs, where the above-threshold regime the mobility is modeled as a function of the gate voltage to a power. An integration procedure is used to extract the device model parameters. In this paper, we complete the extraction procedure to cover all the device operation regions, that is the sub-threshold and above-threshold regimes. The extraction procedure provides in addition the possibility of monitoring the crystallization process of a-Si:H TFTs into polysilicon, which has become a widely used process of fabricating low temperature polysilicon TFTs. The process of polycrystallization manifests itself by a variation and change in sign of one of the model parameters. Extracted parameters can be correlated to input parameters required by AIM-Spice circuit simulator for device modeling. The accuracy of the simulated curves using the extracted parameters is verified with measurements.

Modeling and parameter extraction procedure for nanocrystalline TFTs

Abstract In this paper we present a new procedure to determine model parameters for nanocrystalline TFTs. The method is based on a previous method developed by our group, to extract model parameters of a-Si:H and polysilicon TFTs. The method allows the extraction of the model parameters in the three regions previously observed for nanocrystalline devices, that is, in the subthreshold region and in the two above-threshold regions. These parameters are extracted in a simple and direct way from the experimental measurements, with no need of assigning predetermined values to any other model parameter or using optimization methods. The validity of the procedure is tested for nanocrystalline TFTs, showing a good coincidence between transfer, transconductance and output characteristics calculated using parameter values obtained with our extraction procedure and experimental curves. The proposed method is suitable to be used with circuit simulators such as AIMSpice.

A method to extract mobility degradation and total series resistance of fully-depleted SOI MOSFETs

Free-carrier mobility degradation in the channel and drain/source series resistance are two important parameters limiting the performance of MOS devices. In this paper, we present a method to extract these parameters from the drain current versus gate voltage characteristics of fully-depleted (FD) SOI MOSFETs operating in the saturation region. This method is developed based on an integration function which reduces errors associated with the extraction procedure and on the DC characteristics of MOS devices having several different channel lengths. Simulation results and measured data of FD SOI MOSFETs are used to test and verify the method developed.

A simple procedure to extract the threshold voltage of amorphous thin film MOSFETs in the saturation region

Abstract A technique is presented to extract the threshold voltage of amorphous thin film MOSFETs in the saturation region. The technique is proposed because threshold voltage extraction in amorphous TFTs is different, and in general more complex, than in conventional crystalline bulk devices, since these TFTs exhibit several notable dissimilarities inherent to their characteristics. The saturation drain current follows an m power-law type dependence on gate bias, with an m different from the conventional value of 2. Additionally, a plot of the saturation current as a function of gate bias does not reveal the existence of an inflexion point. The method presented, which extracts the value of the power-law parameter m as well, is based on the use of an auxiliary operator that involves the integration of the drain current as a function of gate voltage. The technique was tested and its accuracy verified using the measured characteristics of an experimental n-channel a-Si:H thin film MOSFET.