A. Giry

High-Performance 15-V Novel LDMOS Transistor Architecture in a 0.25-

The optimization of the small and large signal performances of a radio frequency (RF)-LDMOS is presented via the achievement of a novel LDMOS architecture. Specific process steps are introduced into a 0.25-mum BiCMOS technology and precisely described to realize a fully salicided gate RF-LDMOS architecture. Significant improvement is obtained on the small-signal - fT and Fmax - and power performances while maintaining good dc characteristics

\mu\hbox{m}

This paper presents a complete SPICE sub-circuit model for a lateral double diffused N-MOS (NLDMOS) in a 0.25 m BICMOS technology. The proposed model accurately simulates single and multifinger devices up to geometry sizes used in the final application. The model is validated in DC, AC and large signal conditions. It accounts for all basic LDMOS phenomena such as graded channel, quasi-saturation and self-heating effects. Such study demonstrates that this sub-circuit approach can compete with recent physically based published compact models and even surpass them in terms of flexibility and portability in numerous simulators.

BiCMOS Process for RF-Power Applications

An optimized LDMOSFET and a SiGe:C HBT for PA design, integrated in a BiCMOS technology, are described in this article. Each device of interest, for PA applications, is highlighted via its electrical performance - static, small and large signal.

LDMOS modeling for analog and RF circuit design

In this paper, we present the optimisation of a RF lateral DMOS and its integration in an advanced 0.25 /spl mu/m SiGe:C BiCMOS technology. The proposed device shows excellent characteristics; Ron is around 2.5 /spl Omega/.mm with a BVDS larger than 13 V, f/sub T/ and F/sub max/ reach 21 GHz and 40 GHz respectively. These performances fit wireless RF-power amplifier needs. Integration of such a device in a RF oriented BiCMOS process is a key issue for a SOC approach of wireless circuits.

LDMOSFET and SiGe:C HBT integrated in a 0.25 /spl mu/m BiCMOS technology for RF-PA applications

The improvement of the dynamic performances of a RF LDMOS power amplifier (PA) is presented via the investigation of two device architectures differently optimized: LDMOSo1 and LDMOSo2. The diminution of the capacitance Cds was achieved on LDMOSo1. The reduction of key parameters such as the gate resistance Rg, and the capacitance Cgd was obtained on LDMOSo2. Both optimized architectures could be combined to gain on dynamic performances and complete the LDMOSFET optimization.

Integration and optimisation of a high performance RF lateral DMOS in an advanced BiCMOS technology

LDMOSFET optimization for RF power applications is discussed. Starting from a quite standard transistor, a new architecture has been developed to reach high RF performances without sacrificing DC characteristics. The parasitic elements affecting the RF performances have been identified and reduced. The optimized device presents the following performances: BVds=15V, W.Ron lower than 3 Ohm.mm and f/sub T/ larger than 30 GHz.

Architecture optimization of an N-channel LDMOS device dedicated to RF-power application

Understanding self-heating effect is essential in order to analyze and model the performances of high power transistors [1]. In this paper a new test structure to model thermal coupling on multi-fingered devices is proposed. This structure allows extracting thermal coupling coefficients between different sources. Applied in the case of NLDEMOS devices on SOI technology, a basic model for these coefficients is deduced. Therefore, the thermal profile of the transistor is well reproduced.

NLDMOS RF optimization guidelines for wireless power amplifier applications

A bulk acoustic wave filter, which can be used in EDGE transmitter, is presented in this paper. It attenuates power amplifier harmonic frequencies and out-of-band noise generated by sigma-delta modulator needed in linear architecture. This filter achieves 2.4 dB insertion loss including matching network to 50 Omega and more than 15 dB of return loss. Power handling capability and linearity performance of bulk acoustic wave devices are detailed and satisfy to power application requirements. Antenna mismatch effect has been evaluated using an active load-pull bench. This filter is connected in series to power amplifier to form a prototype of power amplifier module for GSM/EDGE standard in the DCS frequency band. The power amplifier is realized using STMicroelectronics 0.25 mum BiCMOS technology

New self heating structures for thermal coupling modeling on multi-fingered SOI power devices

An asymmetrical spacer LDMOSFET integrated in a 0.25μm BiCMOS technology is presented. Improved RF performances are obtained with this new architecture: fT close to 35GHz with BVds larger than 15V. Process integration strategy is discussed. Impact on the other devices is described.

Linear Transmitter Architecture Using BAW Filter

Power MOSFETs suffer from a strong self-heating effect. This phenomenon is currently modeled with a thermal resistance Rth. Understanding the evolution of the Rth with device scaling is today an important issue. This paper presents an improved test structure for temperature measurements in multifinger LDMOS power devices. This structure allows to access the temperature of every device finger. With this approach, impact of boundary effects and thermal coupling on Rth can be investigated. Measurements results are presented and a basic distributed model is used to reproduce Rth behavior.