Denis Pache

High-Performance 15-V Novel LDMOS Transistor Architecture in a 0.25-

The optimization of the small and large signal performances of a radio frequency (RF)-LDMOS is presented via the achievement of a novel LDMOS architecture. Specific process steps are introduced into a 0.25-mum BiCMOS technology and precisely described to realize a fully salicided gate RF-LDMOS architecture. Significant improvement is obtained on the small-signal - fT and Fmax - and power performances while maintaining good dc characteristics

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A millimeter-wave (mmW) chipset for 77–81 GHz automotive radar has been developed in 0.13μm SiGe HBT technology. This work presents the performances of an integrated Low Noise Amplifier (LNA), a Power Amplifier (PA), a down-converting Mixer, and also a Voltage Controlled Oscillator (VCO). For successful implementation of the circuit, considerations on the reliability of the design have been taken into account. Measurements on all circuits confirm the feasibility of mmW front-end using silicon based technologies for W-band application.

BiCMOS Process for RF-Power Applications

An optimized LDMOSFET and a SiGe:C HBT for PA design, integrated in a BiCMOS technology, are described in this article. Each device of interest, for PA applications, is highlighted via its electrical performance - static, small and large signal.

Millimeter-wave chip set for 77–81 GHz automotive radar application

In this paper, we present the optimisation of a RF lateral DMOS and its integration in an advanced 0.25 /spl mu/m SiGe:C BiCMOS technology. The proposed device shows excellent characteristics; Ron is around 2.5 /spl Omega/.mm with a BVDS larger than 13 V, f/sub T/ and F/sub max/ reach 21 GHz and 40 GHz respectively. These performances fit wireless RF-power amplifier needs. Integration of such a device in a RF oriented BiCMOS process is a key issue for a SOC approach of wireless circuits.

LDMOSFET and SiGe:C HBT integrated in a 0.25 /spl mu/m BiCMOS technology for RF-PA applications

The improvement of the dynamic performances of a RF LDMOS power amplifier (PA) is presented via the investigation of two device architectures differently optimized: LDMOSo1 and LDMOSo2. The diminution of the capacitance Cds was achieved on LDMOSo1. The reduction of key parameters such as the gate resistance Rg, and the capacitance Cgd was obtained on LDMOSo2. Both optimized architectures could be combined to gain on dynamic performances and complete the LDMOSFET optimization.

Integration and optimisation of a high performance RF lateral DMOS in an advanced BiCMOS technology

Both reduction in device sizes and enhanced increase in current densities lead to concern about the impact of the self-heating effect on device electrical characteristics. Moreover, in power transistors applications, devices are connected in parallel, so thermal interaction between devices also has to be considered. In this paper, a nodal model is proposed in order to take into account temperature variation due to self-heating and thermal coupling. This model associated with the HICUM Level 2 version 2.21 compact model is validated thanks to measurements made on specific test structures.

Architecture optimization of an N-channel LDMOS device dedicated to RF-power application

LDMOSFET optimization for RF power applications is discussed. Starting from a quite standard transistor, a new architecture has been developed to reach high RF performances without sacrificing DC characteristics. The parasitic elements affecting the RF performances have been identified and reduced. The optimized device presents the following performances: BVds=15V, W.Ron lower than 3 Ohm.mm and f/sub T/ larger than 30 GHz.

A Nodal Model Dedicated to Self-Heating and Thermal Coupling Simulations

A 142GHz fully-integrated wireless chip-to-chip solution is demonstrated for short range and low power communication. Implemented in 0.13μm SiGe:C BiCMOS technology, the Tx and Rx silicon area including dipole antennas is 0.31mm2. The OOK transceiver achieves a data rate of 14Gbps for a communication distance of 0.6mm with an energy efficiency of 5.7pJ/bit.

NLDMOS RF optimization guidelines for wireless power amplifier applications

This paper describes the techniques to design a SiGe power amplifier (PA) for millimeter wave (mmW) applications. The design methodology of a balanced four-stage common emitter circuit topology was reported. The power amplifier was fully integrated including matching elements and bias circuit. The matching networks use coplanar waveguide (CPW) lines and MIM capacitors. Design considerations including parasitic elements, interconnections, pad model and matching structures are detailed. All these elements are taken into account to optimize the maximum output power. A comparison of the simulated and measured small-signal results is presented up to 110 GHz. The simulated and measured large-signal parameters are shown at 60, 65 and 77 GHz.

A 142GHz fully integrated wireless chip to chip communication system for high data rate operation

Linearity of transmitter is a difficult point to achieve with non constant envelope modulation. The simplest solution is to use a class A power amplifier with sufficient back off, so that sufficient linearity can be obtained but to the detriment of the efficiency. In this paper we present a development of the classical EER architecture where the non constant modulated signal is transformed into a constant one. The envelope variation is restored after an efficient power amplifier with a simple bandpass filter. The key point of this architecture is a full digital 1-bit sigma-delta modulator used to transform the envelope signal into a series of pulses working at frequencies up to 1 GHz