A. Haggag

Understanding SRAM High-Temperature-Operating-Life NBTI: Statistics and Permanent vs Recoverable Damage

The paper shows using deconvolution, SRAM Vmin shift statistics yield a spread that follows Poisson area scaling and a time- and voltage-dependence of t1/6 and V3, respectively. This is demonstrated to be consistent with permanent NBTI shift (Si-H bond breaking) relevant for end-of-life extrapolation. In contrast recoverable NBTI shift (hole trapping/detrapping) is shown to be only a function of stress duty and can be very small for realistic product duties.

Universality of NBTI - From devices to circuits and products

This paper showcases the universality of NBTI and its dependencies on time, bias, temperature, AC frequency and pulse duty cycle across different process integration schemes used in the industry and technology nodes. Strong correlation has been established between device, circuit, and product degradation. Different aspects of variability and variable NBTI in small area devices have been discussed. Features that are important from an industrial perspective are highlighted. Any NBTI model should address these aspects to be considered relevant.

Realistic Projections of Product Fails from NBTI and TDDB

Statistical models for deconvolving the effects of competing mechanisms on product failures are presented. Realistic projections of product fails are demonstrated on high performance microprocessors by quantifying the contribution of NBTI, TDDB and extrinsic fail mechanisms. In particular, it is shown that transistor shifts due to NBTI manifest as population tails in the products minimum operating voltage (Vmin) distribution, while TDDB manifests as single-bit or logic failures that constitute a separate sub-population. NBTI failures are characterized by lognormal statistics combined with a slower degradation rate (Deltat ~ t0.15 -t0.25), in contrast to TDDB failures that follow extreme-value statistics and exhibit a faster degradation rate (DeltaVt ~ t0.5)

Physical model for the power-law voltage and current acceleration of TDDB

As gate voltages scale in ultra-thin gate oxide CMOS and single carrier energy drops below the threshold required for defect generation, we postulate that multiple carrier induced defect generation becomes the dominant degradation mechanism resulting in a power-law voltage and local current acceleration of time-dependent dielectric breakdown (TDDB). Data from multiple technology nodes is presented to corroborate our hypothesis, which is also demonstrated to be consistent with literature reports from several different companies. To the best of our knowledge, this is the first time the power-law local gate current acceleration is proposed in contrast to earlier formulations based on total gate current.

Realistic Projections of Product Fmax Shift and Statistics due to HCI and NBTI

Product Fmax shift is shown to be mainly due to HCI and NBTI. This is because the likelihood of a TDDB event in the product speed path is negligible. An exponential drain current and voltage dependence of HCI and a power-law gate voltage dependence of NBTI are shown to fit the Fmax shift quite well for realistic guardbands.

On the positive channel threshold voltage of metal gate electrodes on high-permittivity gate dielectrics

Factors responsible for the undesirably high values of positive-channel (p-channel) threshold voltage (Vt) in high-κ metal oxide semiconductor transistors are investigated. In silicon/silicon dioxide/hafnium dioxide/metal gate transistors an anomalous nonlinear relationship between the equivalent oxide thickness (EOT) and Vt occurs when the silicon dioxide (SiO2) interface layer is sufficiently thin (<2.3 nm). The deviation from the expected EOT versus Vt behavior is shown to be related to processing temperature, metal work-function, substrate doping type, and thickness of the high-κ material. This result, coupled with charge trapping measurements on samples with different SiO2 interface layer thickness, suggests that the loss of negative fixed charge via the tunneling of trapped electrons to the substrate is a possible explanation for the elevated p-channel Vt.

Flash Oxide Scalability Model and Impact of Program/Erase Method

We discuss flash oxide scalability model of various program/erase methods within the constraint of high performance (fast program/erase times) and high reliability (data retention). We show that HCI programming with FN channel erase (HCI/CE) offers the best scalable solution compared to other common methods, HCI programming with FN edge erase (HCI/EE) and uniform channel FN program erase (UCPE)

Realistic 55nm IC failure in time (FIT) estimates from automotive field returns

We have demonstrated that the raw failure rate from field data decreases much faster than any realistic statistical reliability model due to the artifact that we are also adding parts into the field as time passes. We have shown with a simple mathematical correction we can get real FIT that behaves as expected from realistic statistical reliability model. This methodology for hard failure rate estimation can also be applied for soft failure rate estimation using “NTF” or “No Trouble Found” field returns that are believed marginal parts. Since the next generation technology may be more sensitive to soft failures than the current generation, it is critical to get both hard and soft failure rate estimates, to allow design for reliability decisions.

Fast aging degradation rate prediction during production test

A flow to predict a wafer/dies speed degradation rate without burn-in using ATE tests is presented in this paper. The proposed flow is digital with less than 1μs measurement time per die, allowing it be applied to high volume production test. The accuracy of the proposed flow has been verified by silicon data collected from 5 Freescale® wafers from different production lots. With the proposed flow, the volume of devices requiring burn-in is reduced.

Product failures: Power-law or exponential voltage dependence?

The product failures voltage acceleration has traditionally been modelled with exponential voltage dependence. However with voltage scaling, the voltage acceleration parameter (VAP) in an exponential model has increased as V−1 - as expected for dielectric breakdown in either back-end or front-end. This suggests an exponential model is probably quite conservative and a power-law model may be more appropriate for 90nm and beyond. Even if an exponential model continues to be used, this understanding can help assess the amount of conservatism built in such a model.