S. Kalpat

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.

On the positive channel threshold voltage of metal gate electrodes on high-permittivity gate dielectrics

Factors responsible for the undesirably high values of positive-channel (p-channel) threshold voltage (Vt) in high-κ metal oxide semiconductor transistors are investigated. In silicon/silicon dioxide/hafnium dioxide/metal gate transistors an anomalous nonlinear relationship between the equivalent oxide thickness (EOT) and Vt occurs when the silicon dioxide (SiO2) interface layer is sufficiently thin (<2.3 nm). The deviation from the expected EOT versus Vt behavior is shown to be related to processing temperature, metal work-function, substrate doping type, and thickness of the high-κ material. This result, coupled with charge trapping measurements on samples with different SiO2 interface layer thickness, suggests that the loss of negative fixed charge via the tunneling of trapped electrons to the substrate is a possible explanation for the elevated p-channel Vt.

Defect passivation with fluorine in a Ta/sub x/C/ high-K gate stack for enhanced device threshold voltage stability and performance

Using a novel fluorinated TaxCy/high-k gate stack, we show breakthrough device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern. The novel fluorinated gate stack device exceeds the PBTI and NBTI targets with sufficient margin and has electron mobility comparable to the best polySi/SiON device on bulk Si reported so far

Threshold voltage instability and plasma induced damage of polySi/HfO/sub 2/ devices - positive impact of deuterium incorporation

Device instability is one of the most challenging issues to implement High-K gate dielectric. Incorporation of deuterium during the ALD process effectively improves the interface quality that enhances High-K device stability and reliability. Compared to H/sub 2/O processed HfO/sub 2/ devices, devices with D/sub 2/O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125/spl deg/C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD High-K gate dielectric processing is the final choice.

New Insights on Percolation Theory and the Origin of Oxide Breakdown Thickness and Process Deposition Dependence

In this paper we are using the MVHR model in order to better understand the percolation theory and the impact of gate oxide process conditions.

Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS

We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) CMOS technology. Inversion Tox (Tinv) values of 16Aring/18Aring (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm 2 and enable self-heated drive currents of 850/325muA/mum at 1nA/mum off-state leakage and Vdd=1V (900/340muA/mum non-self-heated). Additionally, the NMOS drive current of 1550 muA/mum (1650muA/mum non-self-heated) at an Ioff = 100nA/mum and Vdd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures

Generalized Models for Optimization of BTI in SiON and High-K Dielectrics

A generalized reliability model of BTI is presented where it is shown that gate stacks with similar interfacial layer lie on the same NBTI vs. E-field universal curve and those with similar bulk layer lie on the same PBTI vs. E-field universal curve. From these universal curves, an optimal gate stack can be derived for which NBTI=PBTI

Mechanism of Gm degradation and comparison of Vt instability and reliability of HfO/sub 2/, HfSiO/sub x/ and HfAlO/sub x/ gate dielectrics with 80 nm poly-Si gate CMOS

To achieve a lower gate leakage in high speed devices at the same equivalent oxide thickness, a major thrust is to replace the SiO/sub 2/ with a thicker dielectric that has a higher dielectric constant. Recently, there has been much interest in hafnium dioxide as a potential high-k gate dielectric as presented in E. P Gusev et a. (2001), B. Barlage et al. (2001), G. Wilk et al. (2001), C. Hobbs et al. (2001), W. Zhu et al. (2001), W. Qi et al. (2000) and B. Lee et al. (1999) due to its high permittivity. However, the polycrystalline microstructure may be undesirable. In order to increase the crystallization temperature, SiO/sub 2/ or Al/sub 2/O/sub 3/ are added to HfO/sub 2/ to form Hf silicates atid Hf aluminates. A systematic study to compare the device characteristics of these three major candidates is needed. In this work, we have compared them in terms of the key challenges of high-K devices such as Gm degradation, Vt instability, and reliability, in devices fabricated with a conventional CMOS process technology according to A. Perera et al. (2000).