Mohamed S. Moosa

Understanding SRAM High-Temperature-Operating-Life NBTI: Statistics and Permanent vs Recoverable Damage

The paper shows using deconvolution, SRAM Vmin shift statistics yield a spread that follows Poisson area scaling and a time- and voltage-dependence of t1/6 and V3, respectively. This is demonstrated to be consistent with permanent NBTI shift (Si-H bond breaking) relevant for end-of-life extrapolation. In contrast recoverable NBTI shift (hole trapping/detrapping) is shown to be only a function of stress duty and can be very small for realistic product duties.

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.

Realistic Projections of Product Fails from NBTI and TDDB

Statistical models for deconvolving the effects of competing mechanisms on product failures are presented. Realistic projections of product fails are demonstrated on high performance microprocessors by quantifying the contribution of NBTI, TDDB and extrinsic fail mechanisms. In particular, it is shown that transistor shifts due to NBTI manifest as population tails in the products minimum operating voltage (Vmin) distribution, while TDDB manifests as single-bit or logic failures that constitute a separate sub-population. NBTI failures are characterized by lognormal statistics combined with a slower degradation rate (Deltat ~ t0.15 -t0.25), in contrast to TDDB failures that follow extreme-value statistics and exhibit a faster degradation rate (DeltaVt ~ t0.5)

Physical model for the power-law voltage and current acceleration of TDDB

As gate voltages scale in ultra-thin gate oxide CMOS and single carrier energy drops below the threshold required for defect generation, we postulate that multiple carrier induced defect generation becomes the dominant degradation mechanism resulting in a power-law voltage and local current acceleration of time-dependent dielectric breakdown (TDDB). Data from multiple technology nodes is presented to corroborate our hypothesis, which is also demonstrated to be consistent with literature reports from several different companies. To the best of our knowledge, this is the first time the power-law local gate current acceleration is proposed in contrast to earlier formulations based on total gate current.

Realistic Projections of Product Fmax Shift and Statistics due to HCI and NBTI

Product Fmax shift is shown to be mainly due to HCI and NBTI. This is because the likelihood of a TDDB event in the product speed path is negligible. An exponential drain current and voltage dependence of HCI and a power-law gate voltage dependence of NBTI are shown to fit the Fmax shift quite well for realistic guardbands.

Product failures: Power-law or exponential voltage dependence?

The product failures voltage acceleration has traditionally been modelled with exponential voltage dependence. However with voltage scaling, the voltage acceleration parameter (VAP) in an exponential model has increased as V−1 - as expected for dielectric breakdown in either back-end or front-end. This suggests an exponential model is probably quite conservative and a power-law model may be more appropriate for 90nm and beyond. Even if an exponential model continues to be used, this understanding can help assess the amount of conservatism built in such a model.

RC triggered active ESD clamps; How should they behave under powered conditions?

Problems with standard RC clamp circuits during powered system level ESD events are reviewed. A new clamp design is presented which employs a proportional triggering scheme that regulates the pad voltage during transient events, rather than simply switching the clamps fully on or off.

Generalized Models for Optimization of BTI in SiON and High-K Dielectrics

A generalized reliability model of BTI is presented where it is shown that gate stacks with similar interfacial layer lie on the same NBTI vs. E-field universal curve and those with similar bulk layer lie on the same PBTI vs. E-field universal curve. From these universal curves, an optimal gate stack can be derived for which NBTI=PBTI

Ultra-thin gate dielectric reliability projections

Phenomenological time-dependent dielectric breakdown (TDDB) and bias-temperature instability (BTI) models are demonstrated to enable reasonably accurate reliability projections for several generations of silicon oxynitride-based transistors and circuits with EOT down to /spl sim/1.3 nm. Furthermore, while reliability and performance can be traded-off by engineering the gate dielectric coupled with device integration, benchmarking of published data suggests that the reliability achievable at each transistor node falls within an intrinsically plausible range for similar dielectric films. A preliminary investigation of high-k dielectric device reliability suggests that a similar methodology can be adopted to project the reliability of scaled high-k films.

The titanic: what went wrong! [integrated circuit design]

We often hear about success stories in EDA. We are all justifiably proud of the impact we collectively make on the overall integrated circuit design and manufacturing machine. It is fair to say, however, the one learns far more from failure than one does from success. In this special session we found several brave practitioners who are willing to talk about problems in business-as-usual EDA. These problems include technology related issues; reliability related issues, power issues and even methodology issues - In short, covering a wide swatch of the EDA domain.