A.I. Akinwande

AlGaAs/InGaAs/GaAs quantum well doped channel heterostructure field effect transistors

The results of experimental and theoretical studies of pseudomorphic AlGaAs/InGaAs/GaAs quantum-well doped-channel heterostructure field effect transistors (QW-DCHFETs) are presented. The channel doping was introduced in two ways: during growth by molecular beam epitaxy or by direct ion implantation. The latter technique may be advantageous for fabrication of complementary DCHFET circuits. Peak transconductances of 471 mS/mm and peak drain currents of 660 mA/mm in 0.6- mu m-gate doped-channel devices were measured. The results show the advantages of the DCHFET over standard heterostructure FET structures and their potential for high-speed IC applications. Self-consisted calculations of the subband structure show that the potential barrier between the quasi-Fermi level in the channel and the bottom of the conduction band in the barrier layer is considerably larger for the doped channel structure than for the structure with an undoped channel. This lowers the thermionic emission gate current of the doped channel device compared to the undoped channel device. >

Complementary III-V heterostructure FETs for low power integrated circuits

The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce the gate leakage currents of n- and p-channel heterostructure FETs. The subthreshold currents and drain-to-gate leakage currents of p-HFETs are also substantially reduced as a result of the high AlAs mole fraction (AlGa)As barrier layer. A 1024*1 bit complementary HFET SRAM with access times as low as 4.6 ns and power dissipation of 34.8 mW has also been demonstrated using this technology.<<ETX>>

Development of static random access memories using complementary heterostructure insulated gate field effect transistor technology

A complementary heterostructure insulated gate field effect transistor (c-HIGFET) technology has been developed which is capable of operating at high speeds with very low static power dissipation. Ring oscillator circuits fabricated using this 1 mu m gate length C-HIGFET technology exhibited very low power dissipation values of down to 67 mu W/gate while maintaining gate delays of approximately 200 ps. In addition, speed-power products of less than 6 fJ have been obtained using these C-HIGFET ring oscillators. The C-HIGFET technology has been used to fabricate 1 kb static random access memories (SRAMs) with yields of over 26% on a 3-inch wafer. Read access times as low as 1.8 ns were obtained for 1 K SRAMs at a power of 650 mW. The 1 K SRAM exhibited a significant reduction in power to 90 mW at a somewhat longer read access time of 4.4 ns.<<ETX>>

A self-aligned gate III-V heterostructure FET process for ultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A 4-b analog-to-digital converter, a 2500-gate 8*8 multiplier/accumulator, and a 4500-gate 16*16 complex multiplier have been demonstrated using enhancement-mode n/sup +/-(Al,Ga)As/MODFETs, superlattice MODFETs, and doped channel heterostructure field-effect transistors (FETs) whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1- mu m gate-length devices, direct-coupled FET logic ring oscillators with realistic circuit structures have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 mu m of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysteresis of less than 1 mV at room temperature. Fully functional 4-b analog-to-digital circuits operating at frequencies up to 2 GHz were obtained. >

High performance complementary logic based on GaAs/InGaAs/AlGaAs HIGFETs

Results for planar, self-aligned gate, complementary, pseudomorphic GaAs-InGaAs-AlGaAs HIGFET devices are presented. The gate leakage is found to be controllable by increasing the AlAs molar fraction in the barrier layer. A planar n-doped layer beneath the InGaAs channel is shown to shift the threshold voltages of the devices and to reduce considerably the output conductance of the p-channel FET. The operation of complementary inverters depends sensitively on the relative values of supply voltage and gate turn-on voltages. Large inverter noise margins are demonstrated, and the power and speed of complementary ring oscillators are discussed.<<ETX>>

GaN solid state electron emitter

We report the first experimental demonstration of a low voltage, room temperature electron emitter that is based on the GaN UV opto-electronic cathode. It consists of an ultra-violet light emitting diode (UV-LED) in direct contact with a photoemitter. The photons generated by the LED have energies 3.4 eV (the bandgap of GaN). The photons cause photoemission of electrons from the surface layer of low workfunction material such as LaB6 or CeB6 (0 = 2.5 eV). The photoemitted electrons are collected by an anode or can be focused. Modulated electron emission is obtained by modulating the LED.

A high performance (Al,Ga)As/GaAs MODFET butterfly adder chip for FFT computation

A report is presented on a butterfly adder chip for high-speed computation of fast Fourier transforms (FFTs). It was fabricated using a 1- mu m self-aligned gate GaAs heterostructure FET (MODFET) technology. The chip receives products from a complex multiplier and generates radix-4 butterfly terms in 32 ns or radix-2 butterfly terms in 16 ns. It also provides the scaling necessary for satisfactory computation of a discrete Fourier transform (DFT) using fixed-point arithmetic. A total of 3800 DCFL gates and over 15700 active devices is required to implement the butterfly adder. The butterfly adder clocks at 262 MHz and it consumes 2.7 W. When used in conjunction with a companion complex multiplier chip of comparable size and other smaller support chips, the butterfly adder allows the computation of a complex DFT on 2048 samples in 100 mu s with a precision of 16 b.<<ETX>>

Electron emission from GaN/LaB/sub 6/ cold cathodes

Summary form only given, as follows. Recent developments in vacuum microelectronics have led to a resurgence of interest into cold cathode emission for applications to a variety of electronic devices. For these new applications, the ideal cold cathode should have the following characteristics: (i) low-voltage operation (5-20 volts); (ii) high current density (5-10 A/cm2); (iii) room temperature operation; and (iv) stable and durable operation. Effective Negative-Electron-Affinity (NEA) and Optoelectronic Cold Cathode (OECC) structures have been fabricated using a combination of the wide-bandgap semiconductors, GaN and AlGaN, and the low work function metal, LaB/sub 6/. In the NEA structure, electrons are injected from an n-type GaN layer into a thin p-type GaN layer. Appropriate design of the p-type thickness, which was guided by Monte Carlo transport simulations, allows some fraction of the injected electrons to arrive at the p-GaN/LaB/sub 6/ interface with enough energy to traverse the thin LaB/sub 6/ layer and emit into vacuum. In the OECC, photons are generated at a p-n junction in GaN. The photons are subsequently absorbed by a LaB/sub 6/ layer, creating electrons with sufficient energy (3.4 eV) to overcome the LaB/sub 6/ work function of /spl sim/2.5 eV. The GaN and LaB/sub 6/ fabrication is discussed in detail. Results of the photoemission from thin LaB/sub 6/ films and electron emission from hybrid and monolithic cold cathodes are discussed.

An asymmetrical lightly doped drain (LDD) self-aligned gate heterostructure field effect transistor

An asymmetrical LDD structure next to the gate was used to improve the breakdown voltages and short-channel characteristics (such as subthreshold currents, threshold voltage uniformity, and output conductance) of self-aligned gate heterostructure FETs (HFETs). This approach decreases impact ionization and increases the breakdown voltage. Previous approaches have created symmetrical lightly doped regions around the gate by using a sidewall spacer, which resulted in high source resistances and transconductance degradation, leading to a tradeoff in transconductance and breakdown voltage. In the LDD HFET, drain-to-source breakdown voltage increased from 4.5 to 12 V and drain-to-gate breakdown voltage improved from 8.8 to 25 V, while the transconductance remained unchanged at 250 mS/mm, as the length of the lightly doped region is varied from 0 to 1 mu m. Experimental data show that the LDD structure eliminates threshold voltage roll off and improves V/sub T/ uniformity across a 3-in. wafer at gate lengths of 0.55 mu m. Further analysis of the subthreshold characteristics and the threshold voltage sensitivity to drain bias shows that the LDD HFET is much less sensitive to drain bias than the conventional HFET. >