Jim Nohava

AlGaAs/InGaAs/GaAs quantum well doped channel heterostructure field effect transistors

The results of experimental and theoretical studies of pseudomorphic AlGaAs/InGaAs/GaAs quantum-well doped-channel heterostructure field effect transistors (QW-DCHFETs) are presented. The channel doping was introduced in two ways: during growth by molecular beam epitaxy or by direct ion implantation. The latter technique may be advantageous for fabrication of complementary DCHFET circuits. Peak transconductances of 471 mS/mm and peak drain currents of 660 mA/mm in 0.6- mu m-gate doped-channel devices were measured. The results show the advantages of the DCHFET over standard heterostructure FET structures and their potential for high-speed IC applications. Self-consisted calculations of the subband structure show that the potential barrier between the quasi-Fermi level in the channel and the bottom of the conduction band in the barrier layer is considerably larger for the doped channel structure than for the structure with an undoped channel. This lowers the thermionic emission gate current of the doped channel device compared to the undoped channel device. >

A 4 kbit synchronous static random access memory based upon delta-doped complementary heterostructure insulated gate field effect transistor technology

Delta-doped pseudomorphic In/sub y/Ga/sub 1-y/As channel complementary heterostructure insulated gate field effect transistor (C-HIGFET) technology has been developed for LSI complementary circuits which exhibit extremely low power dissipation while maintaining the high-speed operation characteristic of III-V heterostructure FETs. Using C-HIGFET ring oscillators with 1 mu m gate lengths, a gate delay of 206 ps was obtained with a gate standby power of only 3.96 mu W/gate and a switching-power-delay product of 145 fJ/gate. The authors have also fabricated fully functional 1 K*4 static random access memories (SRAMs) using this delta-doped C-HIGFET technology. The synchronous 1 K*4 SRAMs operate at a clock frequency of 284 MHz with a total power dissipation of only 183 mW.<<ETX>>

Complementary III-V heterostructure FETs for low power integrated circuits

The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce the gate leakage currents of n- and p-channel heterostructure FETs. The subthreshold currents and drain-to-gate leakage currents of p-HFETs are also substantially reduced as a result of the high AlAs mole fraction (AlGa)As barrier layer. A 1024*1 bit complementary HFET SRAM with access times as low as 4.6 ns and power dissipation of 34.8 mW has also been demonstrated using this technology.<<ETX>>

Development of static random access memories using complementary heterostructure insulated gate field effect transistor technology

A complementary heterostructure insulated gate field effect transistor (c-HIGFET) technology has been developed which is capable of operating at high speeds with very low static power dissipation. Ring oscillator circuits fabricated using this 1 mu m gate length C-HIGFET technology exhibited very low power dissipation values of down to 67 mu W/gate while maintaining gate delays of approximately 200 ps. In addition, speed-power products of less than 6 fJ have been obtained using these C-HIGFET ring oscillators. The C-HIGFET technology has been used to fabricate 1 kb static random access memories (SRAMs) with yields of over 26% on a 3-inch wafer. Read access times as low as 1.8 ns were obtained for 1 K SRAMs at a power of 650 mW. The 1 K SRAM exhibited a significant reduction in power to 90 mW at a somewhat longer read access time of 4.4 ns.<<ETX>>

Vertical cavity surface emitting lasers for spaceborne photonic interconnects

Vertical cavity surface emitting lasers (VCSELs) offer substantial advantages in performance and simplicity of packaging over the edge emitting lasers currently being applied to state-of-the-art photonic interconnects. We have demonstrated operation of VCSELs at cryogenic temperatures and at temperatures as high as 200 degrees Celsius, with a single device operating from minus 55 degrees Celsius to plus 125 degrees Celsius. The devices operate to 14 GHZ and can be operated in excess of 1 GHZ with bias-free operation. Initial radiation tests indicate an order of magnitude improvement in hardness with respect to neutron damage over an LED which is currently used in spaceborne photonic interconnect modules. We also describe the packaging of VCSELs in compact multichip modules. By using passive alignment techniques, optoelectronic devices can be packaged in established multichip module fabrication schemes without adding costly high precision assembly techniques.

VCSEL-based modules for optical interconnects

We present characteristics of 850-nm oxide confined vertical-cavity surface-emitting lasers (VCSELs) developed for applications in optical parallel data links and free- space optical interconnects. Low threshold currents of less than 200 (mu) A, wall-plug efficiencies approaching 30%, operating voltages of less than 2 V for 1 mW of optical power, and operation over a wide temperature range, up to 190 degree(s)C, are demonstrated. We optimized VCSEL arrays for operation at elevated temperatures for use in dense free- space interconnects. Excellent performance uniformity-optical power of 1 +/- 0.1 mW at a drive current of 3 mA-across a 20 X 20 array was achieved at 75 degree(s)C. We integrated 2D top emitting VCSEL arrays with top- illuminated metal-semiconductor-metal detectors for future use with CMOS integrated circuits. We discuss design issues encountered in VCSEL-based modules for optical interconnects.

Gigabit switch using free-space and parallel optical data links for a PCI-based workstation cluster

Communication requirements in high-performance, parallel computing systems continue to increase as the processing nodes within these systems gain processing capability. To support these growing communication requirements, system architecture changes are needed. The use of switched networks rather than bus-based systems and the incorporation of optical interconnects are among proposed solutions to increase overall system performance. Under the VIVACE program, we combine both of these approaches to demonstrate a switched network of 12-Gb/s raw data bandwidth using a 4 Tbit/s bisection bandwidth free-space optically interconnected (FSOI) switch. The optical-interconnect based VIVACE network is accessed by compute nodes through the use of an electrical network interface card (NIC) which provides custom VIVACE protocol conversion in addition to the necessary electrical and optical conversions.

FAST-Net optical interconnection prototype demonstration program

This paper reports progress toward the experimental demonstration of a smart pixel based optical interconnection prototype currently being developed under the Free-space Accelerator for Switching Terabit Networks (FAST-Net) project. The prototype system incorporates 2D arrays of monolithically integrated high- bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs). A key aspect of the FAST-Net concept is that all smart pixels are distributed across a single multi-chip plane. This plane is connected to itself via an optical system that consists of an array of matched lenses (one for each smart pixel chip position) and a mirror. The optical interconnect system implements a global point-to-point shuffle pattern. The interleaved 2D arrays of VCSELs and PDs in the prototype are arranged on a clustered self-similar grid pattern with a closest element pitch of 100 micrometers . The circular VCSEL elements have a diameter of 10 micrometers and the square PDs have an active region that is 50 micrometers wide. These arrays are packaged and mounted on circuit boards along with the CMOS driver, receiver, and FPGA controller chips. Micro-positioning mounts are used to effect alignment that is consistent with current MCM chip placement accuracy. Shuffled optical data links between the multiple ICs have been demonstrated in preliminary evaluation of this system. These results suggest that a multi-Terabit optically interconnected MCM module is feasible.

A self-aligned gate III-V heterostructure FET process for ultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A 4-b analog-to-digital converter, a 2500-gate 8*8 multiplier/accumulator, and a 4500-gate 16*16 complex multiplier have been demonstrated using enhancement-mode n/sup +/-(Al,Ga)As/MODFETs, superlattice MODFETs, and doped channel heterostructure field-effect transistors (FETs) whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1- mu m gate-length devices, direct-coupled FET logic ring oscillators with realistic circuit structures have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 mu m of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysteresis of less than 1 mV at room temperature. Fully functional 4-b analog-to-digital circuits operating at frequencies up to 2 GHz were obtained. >

FAST-Net optical interconnection prototype demonstration

Highly interconnected multiprocessor systems are now performance limited by the backplane interconnection bottleneck associated with planar interconnection technologies. Smart pixel throughput capabilities are projected to exceed I Thitls/cm2 [1] and offer the promise of overcoming the bottlenecks of planar technologies for many types of interconnection-limited multiprocessor problems. Systems that use smart pixel-based free space optical interconnects (FSOI) provide two general dense interconnection capabilities: intelligent parallel data transfer and intelligent parallel data interchange. Optical imaging provides a high throughput approach to linking smart pixel planes for data transfer. In this case the high 110 density of smart pixels may provide a power consumption and size advantage over electronics [2,3]. For data interchange, FSOI provides the additional ability to perform the data partitioning and interleaving useful in space variant link interconnection patterns like the perfect shuffle (PS) [41,which are inherently difficult to implement in planar interconnection technologies. Such patterns are characterized by high BSBW [51. In multi-processor architecture design, there is a direct trade-off between minimum BSBW and latency in a network. It is therefore generally desirable to implement networks with the largest minimum BSBW that can be practically achieved to solve a given problem. The ability of optical elements to interconnect large arrays in space-variant patterns, without crosstalk in the medium, suggests that FSOI techniques are particularly promising for problems with high BSBW. For problems with greater than 1 ThitJsec BSBW (i.e., greater than the capabilities of a single chip) free space optical interconnects have a marked advantage [6,71. Therefore, globally interconnected multi-chip smart pixel based architectures have the potential to reap the full benefits of FSOI. This paper describes the experimental demonstration of a smart pixel based optical interconnection prototype currently being developed under the Free-space Accelerator for Switching Terabit tworks (FAST-Net) project, sponsored by the U.S. Defense Advanced Research Projects Agency. The prototype system incorporates 2-D arrays of monolithically integrated high-bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs). A key aspect of the FAST-Net concept is that all smart pixels are distributed across a single multi-chip plane. This plane is connected to itself via an optical system that consists of an array of matched lenses (one for each smart pixel chip position) and a mirror. The optical interconnect system implements a global point-to-point shuffle pattern. The interleaved 2-D arrays of VCSELs and PDs in the prototype are arranged on a clustered self-similar grid pattern with a closest element pitch of 100 tm. The circular VCSEL elements have a diameter of 10 pm and the square PDs have an active region that is 50 jim wide. These arrays are packaged and mounted on printed circuit boards along with CMOS driver, receiver, and FPGA controller chips. Micro-positioning mounts are used to effect alignment that is consistent with current MCM chip placement accuracy. Shuffled optical data links between the multiple ICs have been demonstrated in preliminary evaluation of this system. These results suggest that a multi-Terabit optically interconnected MCM module is feasible.