A. K. Baliga

Performance analysis of vertical channel organic thin film transistors through 2-D device simulation

This research paper puts forward the electrical behavior of vertical channel organic thin film transistors (V-OTFTs) using organic module of Atlas 2-D numerical device simulator. The electrical characteristics and performance parameters of pentacene based V-OTFT is analyzed. The devices are compared for different line spacing and line width while taking same structural dimensions and electrical properties. The conventional organic thin film transistors (C-OTFT) offers merits of low cost and low temperature fabrication, however, C-OTFTs with long channel length (L) undergo low mobility, low speed and high bias voltage of operation. It is extremely challenging to achieve short channel length in C-OTFTs by using a low cost shadow masking technique. To fulfil this gap, vertical channel structure is investigated for the organic thin film transistor that has proven its potential for fabricating smaller length OTFTs. A vertical channel structure consists of different thin film layers that include three layers of the source, drain and gate in combination with two semiconductor layers. The results observed maximum current Idmax is 24.20, 18.37 and 32.70μA for device 1, 2 and 3 respectively. The 35% and 78% higher current observed for device 3 in comparison to device 1 and device 2 with increase in line-width of 28% w.r.t. to device 1 and 2. Organic-electronics is not a technology competing with inorganic electronics (silicon based devices), but intends for novel-applications that are not feasible or are too costly with MOS transistors.

Performance comparison of pass transistor and CMOS logic configuration based de-multiplexers

This research paper analyzes the performance of De-Multiplexer (De-Mux) using Pass Transistor Logic Configuration (PTLC) and CMOS Logic Configuration (CLC). Furthermore, a comparison between the performances of both the configurations in terms of power dissipation, chip area, power supply and drive current levels are analyzed. Besides this, paper also signifies more than 50% decrement in interconnect lengths, chip area and number of transistors count while using pass transistor logic configuration in comparison to 1:2 De-Mux implemented with CMOS logic configuration. Moreover, reduction in supply voltage and decrement in power dissipation up to 70% is observed in pass transistor logic comparing to CMOS logic.

Performance analysis of dual gate organic thin film transistor through analytical modeling

Enormous research has been done in the field of organic electronics recently. A lot of innovative practices are anticipated for boosting the device and circuit performance. DG-OTFT i.e. dual gate organic thin film transistors are one of these methods that are used for the enhancement of the organic materials based devices and circuits performance. The DG-OTFT augments the operation of the devices and circuits and also makes the devices sturdy. In this research paper depth analyses of the DG-OTFT for different modes of operation (bottom gate, top gate, and dual gate modes) in terms of threshold voltage, drive current, mobility, sub-threshold slope and current on-off ratio is performed. It is observed that as the two channels are formed in DG-OTFT, it results in superior carrier injection that shows significant enhancement in drive current, in the dual gate mode. Evaluation and validation of electrical characteristics and performance parameters of DG-OTFT using PDPP-TNT as organic semiconductor with the reported experimental results is done using state of the are Atlas 2-D by Silvaco Inc. It is a numerical device 2-D TCAD simulator, and it is observed that the simulation results are in close agreement with experimental data.

Impact of Gate Thickness Variation and Dielectric on the Performance of Vertical Organic Thin Film Transistor

This research paper emphasizes on the impact of gate thickness variation and gate dielectric on the performance of an organic static induction-type vertical organic thin film transistor (VOTFT). The electrical behavior of VOTFT is analyzed and performance parameters extraction is carried out using Atlas 2-D numerical device simulator. VOTFTs have high-speed operation in comparison to conventional organic thin film transistor (OTFT) due to shorter channel length that corresponds to thickness of organic semiconductor (OSC) layer. Majority carrier flow from source to drain is controlled by varying gate voltage (V G) applied to Schottky gate electrode. Effect of gate thickness variation is analyzed by varying gate thickness of device from 10 to 50 µm with a step size of 20 µm. Pentacene is used as OSC channel material. A device having additional thin layers of Al2O3 dielectric above and below buried grid-type gate electrode has also been analyzed. The results obtained demonstrate that with 80 % reduction in gate electrode thickness, \({{I_{\text{on}} } \mathord{\left/ {\vphantom {{I_{\text{on}} } {I_{\text{off}} }}} \right. \kern-0pt} {I_{\text{off}} }}\) ratio increases by 48 %. This analysis shows control of drive current (I DS) with gate electrode thickness variation. Device having gate dielectric layers has shown very low off current of 7.01 × 10−9 A that can be attributed to reduction in leakage between gate and source due to use of gate dielectric.

Dual Gate Organic Inverter Circuit Behavior Analysis Based on Diode Load Logic Configuration

The dual gate organic thin film transistor (DG-OTFT), at present is one of the most attractive devices in the field of organic electronics because of its overall better performance in comparison to single gate (SG) organic transistors. Organic electronics have shown good mechanical flexibility, lower temperature fabrication at lower cost in comparison to conventional MOSFET devices. They may not stand as a challenge for the MOS devices as of now but still due to their numerous advantages they are being chosen alternative future candidate by the industries, academia and R and D sections. The dual gate OTFT device analysis and its performance parameters extraction has been done in this paper. Besides this, comparison of different modes of operation of the dual gate device has been made, that justifies our working in the dual gate-based devices and circuits. The dual gate organic inverter circuit that has been analyzed is in the diode load logic (DLL) configuration because of its delay is small and speed of operation is better in comparison with zero-Vgs load logic (ZVLL) configuration.

Performance analysis of vertical channel organic thin film transistors using various OSC materials

This research paper analyzes the performance of vertical channel organic thin film transistor (VOTFT) using state of art industry standard Atlas 2-D numerical device simulator for different channel materials. The basic electrical characteristics of VOTFT are analyzed and parameters extraction is carried out. Lateral channel OTFT offers low-speed and requires high operational voltage due to longer channel length. Thus for high speed operation, VOTFTs are analyzed. These devices have shorter channel length that corresponds to thickness of organic semiconductor (OSC) layer. Organic static induction transistor (OSIT) type structure is used for VOTFT analysis in this research paper. OSITs employ schottky barrier contact between OSC and gate while ohmic contact is formed between OSC and source/drain electrodes. Majority carriers flow from source to drain is controlled by varying gate voltage (VG) applied to schottky gate electrode. Comparative analysis of three OSIT devices for different OSC materials is done by simulation. Device 1 has copper phthalocyanine (CuPc) as OSC material. Device 2 has pentacene as OSC material while Device 3 has pentacene along with ultrathin CuPc layer at source side to increase hole injection. The results obtained demonstrate that Device 3 shows 95.95% and 60.93% higher Ion/off ratio as compared to Device 1 and 2, respectively.

Analysis of bottom gate bottom contact device using floating electrode structure

The bottom gate bottom contact (BGBC) organic transistors are widely used in realization of organic circuits because of its simple fabrication processes, but these devices shown inferior performance. Dual gate (DG) OTFT devices were proposed to overcome from this limitation. However, they enhanced the drive current characteristics however, increased the fabrication steps, cost and size of the devices. Therefore, there is a need to develop BGBC OTFTs in such a way that their performance enhances without any significant change in their size and cost. Floating electrode bottom gate bottom contact organic thin film transistor (FE-BGBC OTFT) structure is proposed and analyzed its performance in this research paper. This structure offers higher carrier accumulation capability and significantly enhances the performance parameters for same biasing and structural parameters. Observed drive current is two times higher for FE-BGBC structure in comparison to conventional BGBC OTFT. Therefore, this structure is suitable for realization of complex digital circuit design.

Performance analysis of dual gate-OTFT with variation in OSC thickness and channel length

Organic electronics is attracting the interest of researchers and industries due to its feather weight, meager cost and mechanical flexibility. Many innovative techniques are anticipated for improving the operation of organic material based devices so that they can be used for high speed applications. One such method is usage of dual gate in the organic thin film transistors (DG-OTFT) that makes the organic devices robust. Dual gate structures have better performance in comparison with the single gate organic thin film transistors (SG-OTFT). In this research paper we have analyzed a DG-OTFT using pentacene as organic semiconductor (OSC) since it has high mobility and adequately high current on/off ratio. Subsequently, the performance parameter analysis of dual gate organic transistor is performed in terms of threshold voltage, drive current, subthreshold slope, current on/off ratio, mobility. Furthermore, comparison of dual gate mode with single gate mode (top and bottom both) is analyzed using organic module of Atlas 2-D numerical device simulator. Besides this, the effect of variation in OSC thickness and channel length is also carried out. It is observed that performance enhances with decrease in OSC thickness from 150nm to 80nm, whereas, length of the channel is varied from 50μm to 10μm at a step size of 10. We have observed that variation of OSC thickness does not affect much the performance of DG-OTFT, while, with 80% reduction in channel length the drive current improves by 83%.

Impact of variation in gate line spacing and active layer thickness on performance of organic static induction transistor

This research paper emphasizes on the impact of variation in gate line spacing (SG) and organic semiconductor (OSC) layer thickness on performance of pentacene based organic static induction transistor (OSIT). Furthermore, complete analysis along with performance parameters extraction is carried out using Atlas 2-D numerical device simulator. Effect of variation in gate line spacing (SG) is analyzed by varying SG of device. Besides this, effect of variation in OSC layer thickness is analyzed of OSIT device. This analysis shows that current conduction can be controlled effectively with smaller gate line spacing due to better coverage of channel region by depletion layer in off state. Analysis of variation in OSC layer thickness demonstrates that smaller reduction in OSC layer, have large improvement in Ion/Ioff ratio. Therefore, drive current of an OSIT can be controlled at optimum thickness of OSC layer.

Performance analysis of dual gate OTFT using different gate dielectric materials

Significant research work is carried out at present for performance enhancement of organic devices and circuits that has become now an alternative candidate of flexible electronics technology. This research paper includes the depth analysis of a dual gate organic thin film transistor (DG-OTFT) because it has better performance in comparison to single gate OTFT structure. Subsequently, the impact of different materials for top gate dielectric is carried out, wherein, one device uses Parylene as top insulator while other device uses plasma-enhanced atomic layer deposition (PEALD) aluminum oxide (Al2O3). The performance analysis of both DG-OTFT in terms of subthreshold slope, threshold voltage, current on-off ratio and mobility is carried out using Atlas 2-D numerical device simulator. Device with Parylene organic dielectric material is observed to have better performance in comparison to its counterpart. Besides this, a comparison of performance in various modes of dual gate OTFT operation is discussed in this paper. It is observed that the dual gate mode operation shows better performance in comparison to other modes of operation.