Poornima Mittal

Channel length variation effect on performance parameters of organic field effect transistors

This research paper analyzes, finite element based two dimensional device simulations for top and bottom contact organic field effect transistors (OFETs) by considering uniform and non-consistent mobility regions. To model the morphological disorder in bottom contact structure, some calibrated standards for simulation is developed viz. by considering variable low mobility regions near the contacts. An analytical model is developed, by considering contact resistance and field dependent mobility. The effect of channel length variation (5-40@mm) on performance parameters is highlighted for both the structures. Subsequently, results shows only 1% change in current for bottom contact with 0.5@mm and 1@mm low mobility region near the contacts, due to dominant contact resistance, whereas, linear dependency is observed for other simulated structures. The top contact device shows 0.43cm^2/Vs saturation mobility at 5@mm and 13% decrease up to 20@mm and afterwards constant behavior is noticed, whereas low mobility is extracted in bottom contact devices and shows 10-20% increase in both the mobilities for increasing channel length from 5 to 40@mm. For top and bottom devices, total 65% and 62% decrease in contact resistance is observed for increasing gate voltage from -1.8V to -3V and this percentage reduces for increasing the length of low mobility region. Further, we have evaluated 13%, 40% and 78% increase in the trap density, while proceeding for 0.25@mm, 0.5@mm and 1@mm low mobility region in the bottom contact structure.

Organic Thin Film Transistor Architecture, Parameters and their Applications

Organic Thin Film Transistors (OTFTs) are promising devices for future development of variety of low-cost and large-area electronics applications such as flexible displays. This paper analyzes the performance of OTFT made of several organic semi conducting and insulating materials and further discusses their applications. Analysis of previous research work demonstrates that the mobility in OTFT decreases when the product of semi conducting film thickness and gate capacitance per unit area increases. The decrease is specified by a power law function with parameters for several organic semiconductors. OTFT characteristics have undergone spectacular improvements during the last few years. This paper explores the effect of variation of channel length from 40 nm to 20 nm on drain current for pentacene bottom contact structure. Variations in these quantities maps to variations in the electrical behaviour of devices. It has been found that drain current increases due to decrease in length of organic thin film conducting channel. It reviews recent progress in parameter properties for device designs and applications related to OTFTs. The performance of OTFTs is evaluated in terms of mobility, on/off current ratio, threshold voltage and sub threshold slope. This paper thoroughly discusses the overall performance and applications of OTFTs in various fields.

Characteristics and applications of Polymeric Thin Film Transistor: Prospects and challenges

Polymeric Thin Film Transistors (PTFTs) have undergone extraordinary improvements during the last decade. PTFTs which are also termed as Organic Thin Film Transistor (OTFT) are promising devices for future development of variety of low-cost and large-area electronics applications such as active-matrix displays and flexible micro-electronics. Organic transistors show high mobility, high-speed and high-current characteristics and are suitable for driver elements of flexible displays. This paper reviews recent progress in materials, fabrication processes, advances in device designs and applications related to PTFTs/ OTFTs. The performance of PTFTs/OTFTs is evaluated in terms of on/off current ratio, threshold voltage, subthreshold slope, power dissipation, switching time, driving capability and effective mobility. Various analytical models such as charge transport phenomena in organic solids and resulting models of PTFTs/OTFTs are reviewed. The paper thoroughly discusses the applications of OTFTs in various fields. Prospects, challenges and limitations are also discussed. Recently, polymer thin film transistors area has emerged as a field of intense research activities with emphasis on fundamental concepts and practical applications.

Impact of source and drain contact thickness on the performance of organic thin film transistors

This paper analyzes the impact of source (ts) and drain (td) contact thicknesses on top contact (TC) and bottom contact (BC) organic thin film transistors (OTFTs) with a gate in the bottom, using a benchmarked industry standard Atlas 2-D numerical device simulator. The parameters including drive current (Ids), mobility (μ), threshold voltage (Vt) and current on-off ratio (ION/IOFF) are analyzed from the device physics point of view on different electrode thicknesses, ranging from infinitesimal to 50 nm, for both top and bottom contact structures. Observations demonstrate that the performance of the BC structure is more affected by scaling of ts/d in comparison to its counterpart. In the linear region, the mobility is almost constant at all the values of ts/d for both structures. However, an increment of 18% and 83% in saturation region mobility is found for TC and BC structures, respectively with scaling down ts/d from 50–0 nm. Besides this, the current on-off ratio increases more sharply in the BC structure. This analysis simplifies a number of issues related to the design and fabrication of organic material based devices and circuits.

Prospects and Limitations of Organic Thin Film Transistors (OTFTs)

Organic Transistor (OT) modeling, fabrication and applicability has undergone remarkable progress during last ten years. Organic Thin Film Transistors (OTFTs) have received significant attention recently because of their considerable utility. They can be fabricated at lower temperature and significantly reduced cost as compared to Hydrogenated Amorphous Silicon Thin Film Transistors (a-Si: H TFTs). Fabrication of OTFTs at low temperature allows utilization of wide range of substrates, thereby permitting usage of organic transistors as future candidate for many low-cost electronics applications that require flexible polymeric substrates such as RFID tags, smart cards, electronic paper, and active matrix flat panel displays. This paper provides detailed insight of OTFTs, their operating principles, device materials and various structures such as Top Gate Top Contact (TGTC), Top Gate Bottom Contact (TGBC), Bottom Gate Top Contact (BGTC) and Bottom Gate Bottom Contact (BGBC). Although OTFTs find tremendous and widespread applications, but is marred by few limitations related to factors such as speed, compatibility, stability, degradability and variability. This paper comprehensively discusses the performance and limitations of OTFTs.

Performance analysis of vertical channel organic thin film transistors through 2-D device simulation

This research paper puts forward the electrical behavior of vertical channel organic thin film transistors (V-OTFTs) using organic module of Atlas 2-D numerical device simulator. The electrical characteristics and performance parameters of pentacene based V-OTFT is analyzed. The devices are compared for different line spacing and line width while taking same structural dimensions and electrical properties. The conventional organic thin film transistors (C-OTFT) offers merits of low cost and low temperature fabrication, however, C-OTFTs with long channel length (L) undergo low mobility, low speed and high bias voltage of operation. It is extremely challenging to achieve short channel length in C-OTFTs by using a low cost shadow masking technique. To fulfil this gap, vertical channel structure is investigated for the organic thin film transistor that has proven its potential for fabricating smaller length OTFTs. A vertical channel structure consists of different thin film layers that include three layers of the source, drain and gate in combination with two semiconductor layers. The results observed maximum current Idmax is 24.20, 18.37 and 32.70μA for device 1, 2 and 3 respectively. The 35% and 78% higher current observed for device 3 in comparison to device 1 and device 2 with increase in line-width of 28% w.r.t. to device 1 and 2. Organic-electronics is not a technology competing with inorganic electronics (silicon based devices), but intends for novel-applications that are not feasible or are too costly with MOS transistors.

Organic thin film transistors characteristics parameters, structures and their applications

The differences in drain current and drain voltage characteristics of top gate and bottom gate Organic Thin Film Transistor (OTFT) structures are analyzed by two dimensional numerical device simulators. Further discussion shows different characteristics parameters of OTFTs. Transistor based on organic semiconductor (conjugated or conducting polymers) as active layer to manage electric current flow is known as OTFTs. The performance parameters of OTFTs are evaluated from output and transfer characteristics of different structures of OTFTs. Device characteristics parameters have been evaluated in terms of drain current, mobility, on/off current ratio, threshold voltage, subthreshold slope and transconductance. OTFTs are considered as promising device for future development of their various applications in the areas of low-cost and large-area electronics. Further this paper thoroughly discusses the overall performance and applications of OTFTs in various fields.

Design and analysis of ALU: Vedic mathematics approach

This paper presents a technique called “Vedic Mathematics” for designing the multiplier that is fast as compared to other multipliers based on mathematical techniques that have been in practice for a long time. A processors speed depends prominently on its multiplier as multipliers are used in various fields where processing of some signal is essential. Here, a high-speed 8×8 bit multiplier is designed and analyzed which is based on the Vedic multiplier mechanism. This architecture is diverse from the conservative method of employing product of two numbers accomplished by the process of add and shift. The proposed method is efficient and fast, wherein the processing involves the vertical and crossed multiplication of precedent Vedic mathematics. It incorporates the partial products followed by additive result that too in a single step. The method and architecture decreases the complexity of the design of multiplier. The projected Vedic multiplier is coded in a high level digital language (VHDL) followed by synthesization using EDA tool, XilinxISE12.2i. Finally, a comparison is made between results based on Vedic methodology and stereotyped multipliers. Surprisingly, the performance is found superior in terms of delay and thereby efficiency too. Since, Vedic mathematics technique exhibits low time processing thereby the present work will be helpful in preceding a step towards high speed multipliers and processors.

Top and Bottom Gate Polymeric Thin Film Transistor Analysis through Two Dimensional Numerical Device Simulation

This paper presents detailed analysis of bottom and top gate Polymeric/ Organic Thin Film Transistors (PTFTs/OTFTs) structures through two dimensional numerical device simulations. Further discussion shows various characteristics and properties of bottom gate bottom contact (BGBC), bottom gate top contact (BGTC), top gate top contact (TGTC) and top gate bottom contact (TGBC) Polymeric Transistors (PTs). Transistor based on organic semiconductor conducting polymers or small molecules used as active layer is identified to manage electric current flow which is known as PTFTs/OTFTs. The performance parameters of PTFTs are evaluated from output and transfer characteristics of different structures. Device characteristics parameters have been evaluated in terms of on/off current ratio, threshold voltage, field effect mobility, sub threshold slope, capacitance, transconductance and drive current. PTFTs/OTFTs are considered as promising switching device for future development of low-cost and large-area electronics applications such as flexible displays, organic memory, digital circuits and Sensors.

Performance comparison of pass transistor and CMOS logic configuration based de-multiplexers

This research paper analyzes the performance of De-Multiplexer (De-Mux) using Pass Transistor Logic Configuration (PTLC) and CMOS Logic Configuration (CLC). Furthermore, a comparison between the performances of both the configurations in terms of power dissipation, chip area, power supply and drive current levels are analyzed. Besides this, paper also signifies more than 50% decrement in interconnect lengths, chip area and number of transistors count while using pass transistor logic configuration in comparison to 1:2 De-Mux implemented with CMOS logic configuration. Moreover, reduction in supply voltage and decrement in power dissipation up to 70% is observed in pass transistor logic comparing to CMOS logic.