A. Leona

A time-over-threshold machine: the readout integrated circuit for the BABAR Silicon Vertex Tracker

A low-noise, mixed-signal, 128-channel CMOS integrated circuit containing the complete readout electronics for the BABAR Silicon Vertex Tracker has been developed. The outstanding feature of the present implementation is the ability to perform simultaneously low-level signal acquisition, derandomizing data storage, sparsification and data transmission on a single monolithic chip. The signals from the detector strips are amplified, shaped by a CR-RC/sup 2/ filter with digitally selectable peaking time of 100 ns, 200 ns, 300 ns, or 400 ns, and then presented to a time-over-threshold processor to implement a compression type analog-to-digital conversion. The digital information is stored, sparsified and read out through a serial link upon receipt of a command. The digital section operates from a 60 MHz incoming clock. Noise measurements at 200 ns peaking time and 3.5 mW total power dissipation per channel yield an equivalent noise charge of 600 el. rms at 12 pF added source capacitance. The chip measures 5.7 mm/spl times/8.3 mm and contains 330 k transistors. The first full-scale prototype was fabricated in a radiation soft 0.8 /spl mu/m, 3-metal CMOS process. The same circuit is now being fabricated in an analogous radiation hard technology.

Noise limits in a front-end system based on time-over-threshold signal processing

Abstract An analog signal processor based on the Time-over-Threshold (ToT) range compression is employed in the front-end section of the readout chip of the microstrip vertex detector for the BaBar experiment. The paper, after describing the circuit solutions that have been adopted to optimize the ToT operation, focuses on the noise aspects of the ToT processor. Comparisons are made between the signal-to-noise ratio in the linear processor preceding the ToT circuit and that obtained at the output of the entire analog channel including the ToT function.

The analog front-end section of the BaBar silicon vertex tracker readout IC

This paper describes the evolution in the analog section of the vertex detector readout chip for the BaBar experiment. In order to optimize its behaviour, an intermediate chip reproducing the analog part alone was developed and tested. It provided some useful design hints that provided the basis for the final conception of the analog front-end as it is now operational in the complete BaBar chip.

Functional characteristics and radiation tolerance of AToM, the front-end chip of BaBar silicon vertex tracker

The readout chip designed to process the microstrip signals in the BaBar silicon vertex tracker (SVT), after being realized twice in a radsoft technology has been transferred into the final radhard process. So far the circuit has gone through four different radhard submissions, one aiming at providing a preliminary insight into the characteristics of the radhard chip, the other ones constituting pre-production and production runs. Chips from these submissions have undergone a thorough set of tests addressing functional aspects, noise parameters and effects of radiation on signal and noise behavior. The present paper discusses the results of these tests and describes the final version of the circuit which has been proven to successfully meet the experiment requirements.

Design hints for best noise and signal behaviour in DMILL amplifiers

Abstract As a result of a research and development activity on monolithic low noise structures based on the DMILL process, some basic design criteria have been drawn. These criteria are presented in this paper to show how they can lead to preamplifiers of outstanding noise characteristics that suit applications ranging from calorimetry to tracking and radiation spectrometry.

AToM: the front-end chip for the BaBar silicon vertex tracker detector

This paper describes the readout integrated circuit of the silicon vertex tracker detector for the BaBar experiment at Stanford Linear Accelerator Center. A unique feature of the circuit is its ability to simultaneously amplify and shape signals from 128 microstrip detectors, retain the charge information during the level 1 trigger latency time, and perform sparsification and data transmission over a single serial line. The circuit is composed of two sections. In the analog section signals from the detectors are amplified through a charge sensitive loop, shaped by a CR-RC/sup 2/ filter with digitally selectable peaking time (100 ns, 200 ns, 300 ns or 400 ns) and finally compared to a digitally selectable threshold to perform a range compression. The digital section contains a 193 deep digital pipeline, a three level back-end buffer, two DACs for threshold and calibration voltages, a global control section and a command decoder. The digital section operates at 60 MHz clock speed. Noise measurements at 200 ns peaking time and 3.5 mW total power dissipation per channel yield an equivalent noise charge of 600 el. rms at 12 pF added source capacitance. The chip measures 5.7 mm/spl times/8.3 mm and contains 330 K transistors. A full-scale prototype was fabricated in a 0.8 /spl mu/m, 3-metal rad-soft CMOS process, a second prototype has been characterized using a compatible rad-hard process by Honeywell and the pre-production chip is currently being fabricated.