I. Kipnis

A time-over-threshold machine: the readout integrated circuit for the BABAR Silicon Vertex Tracker

A low-noise, mixed-signal, 128-channel CMOS integrated circuit containing the complete readout electronics for the BABAR Silicon Vertex Tracker has been developed. The outstanding feature of the present implementation is the ability to perform simultaneously low-level signal acquisition, derandomizing data storage, sparsification and data transmission on a single monolithic chip. The signals from the detector strips are amplified, shaped by a CR-RC/sup 2/ filter with digitally selectable peaking time of 100 ns, 200 ns, 300 ns, or 400 ns, and then presented to a time-over-threshold processor to implement a compression type analog-to-digital conversion. The digital information is stored, sparsified and read out through a serial link upon receipt of a command. The digital section operates from a 60 MHz incoming clock. Noise measurements at 200 ns peaking time and 3.5 mW total power dissipation per channel yield an equivalent noise charge of 600 el. rms at 12 pF added source capacitance. The chip measures 5.7 mm/spl times/8.3 mm and contains 330 k transistors. The first full-scale prototype was fabricated in a radiation soft 0.8 /spl mu/m, 3-metal CMOS process. The same circuit is now being fabricated in an analogous radiation hard technology.

A 16-channel charge sensitive amplifier IC for a PIN photodiode array based PET detector module

A 16-channel integrated circuit charge sensitive preamplifier has been developed for a PET detector module that uses an 8/spl times/8 array of PIN photodiodes to identify the crystal of interaction. The amplifier, which is made using 1.2 /spl mu/m CMOS technology, produces an output of 100 mV per 1000 e/sup -/ input, and its noise performance is optimized for 10 pF detector capacitance. The rise time, fall time, bias current through the first FET, and detector current compensation are each controlled by a dc current applied to the 2 mm square chip. The Johnson noise (e/sup -/ fwhm at 1 /spl mu/s peaking time) is 173+13C, where C is the input capacitance in pF, and the shot noise (e/sup -/ fwhm) is 16.4/spl radic/(IT), where I is the detector dark current in pA and T is the amplifier shaping time in /spl mu/s. With this amplifier, the target noise of 300 e/sup -/ fwhm can nearly be met with 300 /spl mu/m depletion thickness photodiodes (3 pF, 200 pA per 3/spl times/3 mm element). >

A high rate, low noise, X-ray silicon strip detector system

An X-ray detector system, based on a silicon strip detector wire-bonded to a low noise charge-sensitive amplifier integrated circuit, has been developed for synchrotron radiation experiments which require very high count rates and good energy resolution. Noise measurements and X-ray spectra were taken using a 6 mm long, 55 /spl mu/m pitch strip detector in conjunction with a prototype 16-channel charge-sensitive preamplifier, both fabricated using standard 1.2 /spl mu/m CMOS technology. The detector system currently achieves an energy resolution of 350 eV FWHM at 5.9 keV, 2 /spl mu/s peaking time, when cooled to -5/spl deg/C. >

Signal processing in the front-end electronics of BaBar vertex detector

Abstract The microstrip vertex detector in BaBar experiment will be read out by a purposely designed front-end chip. The chip performs amplification and analog-to-digital conversion to retain the information of the charge induced on the readout strips. It stores the digital data during the trigger latency time and associates the incoming trigger with the relevant hit data. Data are buffered and sent off in sparsified form when a readout command is received. The present paper discusses the signal processing performed by the chip.

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker The IC was designed and tested at LBL and was fabricated using AT&Ts CBIC-U2, 4 GHz f/sub /spl tau// complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 /spl mu/m pitch double-sided silicon strip detector. The chip measures 6.8 mm/spl times/3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. RMS at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a /spl Phi/=10/sup 14/ protons/cm/sup 2/ have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process. >

The analog front-end section of the BaBar silicon vertex tracker readout IC

This paper describes the evolution in the analog section of the vertex detector readout chip for the BaBar experiment. In order to optimize its behaviour, an intermediate chip reproducing the analog part alone was developed and tested. It provided some useful design hints that provided the basis for the final conception of the analog front-end as it is now operational in the complete BaBar chip.

Signal-to-noise in silicon microstrip detectors with binary readout

We report the results of a beam test at KEK using double-sided AC-coupled silicon microstrip detectors with binary readout, i.e., a readout where the signals are discriminated in the front-end electronics and only the hit location as kept. For strip pitch between 50/spl mu/ and 200/spl mu/, we determine the efficiency and the noise background as function of threshold setting. This allows us to reconstruct the Landau pulse height spectrum and determine the signal/noise ratio. In addition, the threshold/noise ratio necessary for operation with low occupancy is determined. >

Progress in multi-element silicon detectors for synchrotron XRF applications

Multi-element silicon strip detectors, in conjunction with integrated circuit pulse-processing electronics, offer an attractive alternative to conventional lithium-drifted silicon and high purity germanium detectors for high count rate, low noise synchrotron X-ray fluorescence applications. We have been developing these types of detectors specifically for low noise synchrotron applications, such as extended X-ray absorption fine structure spectroscopy, microprobe X-ray fluorescence and total reflection X-ray fluorescence. The current version of the 192-element detector and integrated circuit preamplifier, cooled to -25/spl deg/C with a single-stage thermoelectric cooler, achieves an energy resolution of <200 eV full width of half maximum (FWHM) per channel (at 5.9 keV, 2 /spl mu/s peaking time), and each detector element is designed to handle /spl sim/20 kHz count rate. The detector system will soon be completed to 64 channels using new application specific integrated circuit amplifier chips, new CAMAC analog-to-digital converters recently developed at Lawrence Berkeley National Laboratory, CAMAC histogramming modules, and Macintosh-based data acquisition software. We report on the characteristics of this detector system, and the work in progress towards the next generation system.

An efficient digital X-ray imaging system with high spatial resolution and robust energy sensitivity

A one-dimensional array of X-ray detection pixels is formed by orienting a silicon strip detector edge on, with its strips parallel to the X-ray beam. Spatial resolution is governed by the pixel size, defined by the silicon thickness and strip pitch. The detector orientation presents a large apparent depth for X-ray conversion, resulting in a high quantum efficiency. Coarse, but very stable X-ray energy determination is made by counting the number of conversions as a function of depth in each pixel: The strips (pixels) are subdivided into segments, each sampling a different conversion interval. Custom CMOS ICs provides each detector element with an independent low noise preamp, shaper, comparator and 16-bit counter. During the acquisition phase, each channel counts X-ray conversions, at rates in the 1 MHz range. Readout consists of uploading the counter sums (8 bytes/pixel) to the host computer.

Beam Test Of The SDC Double-sided Silicon Strip Detector

A beam test was executed to evaluate the behavior of the first prototype radiation-hard double-sided silicon microstrip sensor for the SDC silicon tracking system. Pions of 4 GeV/c in a test bcamline at KEK illuminated three planes of detectors. Thc signals wcrc amplified, shaped, and discriminated with TEKZ bipolar analog LSIs, and the on-off levels were sampled at l0MHz clock with CMOS digiwl LSIs, asynchronously with beam triggers. The detectors were rotated in null and 1 .O Tesla magnetic fields. The efficiencies were found to be 98-9996. The position resolutions were 12.5pm. where the multi-strip hit fraction was 30-40%. There was no essential difference in the performance of the pand the n-sides. The multi-strip hit fraction showed a clear rotation and magnetic-field dependence. From the angles where the fractions were minimum in the 1T magnetic field, the Hall mobilities of the electrons and holes were obtained to be 1391k43 (clcctrons) and 325f30 (holes) cm2/Vs.