F. Faccio

Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects

We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELTs) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASICs designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELTs: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of ICs conceived with this design approach are finally drawn.

Radiation-induced edge effects in deep submicron CMOS transistors

The study of the TID response of transistors and isolation test structures in a 130 nm commercial CMOS technology has demonstrated its increased radiation tolerance with respect to older technology nodes. While the thin gate oxide of the transistors is extremely tolerant to dose, charge trapping at the edge of the transistor still leads to leakage currents and, for the narrow channel transistors, to significant threshold voltage shift-an effect that we call Radiation Induced Narrow Channel Effect (RINCE).

Computational method to estimate Single Event Upset rates in an accelerator environment

We present a new method to estimate Single Event Upsets (SEU) in a hadron accelerator environment, which is characterized by a complicated radiation spectrum. Our method is based on first principles, i.e. an explicit generation and transport of nuclear fragments and detailed accounting for energy loss by ionization. However, instead of simulating also the behaviour of the circuit, we use a Weibull fit to experimental heavy-ion SEU data in order to quantify the SEU sensitivity of the circuit. Thus, in principle, we do not need to know details about the circuit and our method is almost free of adjustable parameters ‐ we only need a reasonable guess for the Sensitive Volume (SV) size. We show by a comparison with experimental data that our method predicts the SEU cross sections for protons rather accurately. We then indicate with an example how our method could be applied to predict SEU rates at the forthcoming LHC experiments.

Noise characterization of a CMOS technology for the LHC experiments

Abstract After having reviewed the main noise sources in an MOS transistor the paper presents results about the noise performance of a 0.25 μm CMOS technology which is being extensively used to design radiation tolerant ASICs for the LHC experiments (the Large Hadron Collider at present under construction at CERN). The 1/ f and white noise are studied for n- and p-channel devices with five different gate lengths, in weak, moderate and strong inversion and for different drain to source and bulk to source biases. The noise degradation is measured after irradiation with 10 keV X-rays and after annealing. The results are commented in view of the use of these transistors in low-noise front-end circuits.

A radiation tolerant gigabit serializer for LHC data transmission

In the future LHC experiments, some data acquisition and trigger links will be based on Gbit/s optical fiber networks. In this paper, a configurable radiation tolerant Gbit/s serializer (GOL) is presented that addresses the high-energy physics experiments requirements. The device can operate in four different modes that are a combination of two transmission protocols and two data rates (0.8 Gbit/s and 1.6 Gbit/s). The ASIC may be used as the transmitter in optical links that, otherwise, use only commercial components. The data encoding schemes supported are the CIMT (G-Link) and the 8B/10B (Gbit-Ethernet & Fiber Channel). To guarantee robustness against total dose irradiation effects over the lifetime of the experiments, the IC was fabricated in a standard 0.25 μm CMOS technology employing radiation tolerant layout practices.

Single event effects in static and dynamic registers in a 0.25 /spl mu/m CMOS technology

We have studied single event effects in static and dynamic registers designed in a quarter micron CMOS process. In our design, we systematically used guardrings and enclosed (edgeless) transistor geometry to improve the total dose tolerance. This design technique improved both the SEL and SEU sensitivity of the circuits. Using SPICE simulations, the measured smooth transition of the cross-section curve between LET threshold and saturation has been traced to the presence of four different upset modes, each corresponding to a different critical charge and sensitive area. A new architecture to protect the content of storage cells has been developed, and a threshold LET around 89 MeV cm/sup 2/ mg/sup -1/ has been measured for this cell at a power supply voltage of 2 V.

Optical readout and control systems for the CMS tracker

The Compact Muon Solenoid (CMS) Experiment will be installed at the CERN Large Hadron Collider (LHC) in 2007. The readout system for the CMS Tracker consists of /spl sim/10 million individual detector channels that are time-multiplexed onto /spl sim/40000 uni-directional analogue (40MS/s) optical links for transmission between the detector and the /spl sim/65m distant counting room. The corresponding control system consists of /spl sim/2500 bi-directional digital (40Mb/s) optical links based upon the same components as far as possible. The on-detector elements (lasers and photodiodes) of both readout and control links will be distributed throughout the detector volume in close proximity to the silicon detector elements. For this reason, strict requirements are placed on minimal package size, mass, power dissipation, immunity to magnetic field and radiation hardness. It has been possible to meet the requirements with the extensive use of commercially available components with a minimum of customization. The project has now entered its volume production phase after successful completion of technical feasibility. Components have been identified that meet both the stringent analogue performance targets and are sufficiently radiation-hard for use in the CMS Tracker, where lifetime radiation exposure is expected to reach /spl sim/3.4/spl times/10/sup 14//cm/sup 2/ fluence and /spl sim/150kGy dose. Analogue and digital system performance, as well as the component radiation hardness and quality assurance procedures, are reviewed this paper.

Total ionizing dose effects in shallow trench isolation oxides

The peaked evolution of leakage current with total ionizing dose observed in transistors in 130 nm generation technologies is studied with field oxide field effect transistors (FOXFETs) that use the shallow trench isolation as gate oxide. The overall radiation response of these structures is determined by the balance between positive charge trapped in the bulk of the oxide and negative charge in defect centers at its interface with the silicon substrate. That these are mostly interface traps and not border traps is demonstrated through dynamic transconductance and variable-frequency charge-pumping measurements. These interface traps, whose formation is only marginally sensitive to the bias polarity across the oxide, have been observed to anneal at temperatures as low as 80 °C. At moderate or low dose rate, the buildup of interface traps more than offsets the increase in field oxide leakage due to oxide-trap charge. Consequences of these observations for circuit reliability are discussed.

G-link and gigabit Ethernet compliant serializer for LHC data transmission

Gbit/s data transmission links will be used in several LHC detectors in trigger and data acquisition systems. In these experiments, the transmitters will be subject to high radiation doses over the lifetime of the experiments. In this work, a radiation tolerant transmitter ASIC is described. The IC supports two standard protocols, the G-link and the Gbit-Ethernet, and sustains transmission of data at both 800 Mbit/s and 1.6 Gbit/s. The ASIC was implemented in a mainstream 0.25 /spl mu/m CMOS technology employing radiation tolerant layout practices. A 1.2 Gbit/s prototype with reduced functionality was tested. The ASIC behavior under total dose irradiation as well as its susceptibility to single event upsets was studied and the results are reported here.

Deep submicron CMOS technologies for the LHC experiments

Abstract The harsh radiation environment at the Large Hadron Collider (LHC) requires radiation hard ASICs. This paper presents how a high tolerance for total ionizing dose can be obtained in commercial deep submicron technologies by using enclosed NMOS devices and guard rings. The method is explained, demonstrated on transistor and circuit level, and design implications are discussed. A model for the effective W/L of an enclosed transistor is given, a radiation-tolerant standard cell library is presented, and single event effects are discussed.