A. Neyer

Demonstrating optoelectronic interconnect in a FPGA-based prototype system using flip-chip mounted 2D arrays of optical components and 2D POF-ribbon arrays as optical pathways

Architectural studies have identified field-programmable gate arrays (FPGA) as a class of general-purpose very large scale integration components that could benefit from the introduction at the logic level of state-of-the-art massively parallel optical inter-chip interconnections. In this paper, we present a small-scale optoelectronic multi-FPGA demonstrator in which three optoelectronic enhanced FPGAs are interconnected by 2D Plastic Optical Fiber (POF) ribbon arrays. The full-custom FPGA chips consisting of an 8 X 8 array of very simple programmable logic cells are equipped with two optical sources and two receivers per FPGA cell yielding a maximum of 256 optical links per chip. The optical links are designed for signaling rates of 80 to 100 Mbit/s (160 to 200 Mbaud using Manchester coded data) compatible with the maximum clock frequency of the, in 0.6 micrometers CMOS implemented, FPGA chips. The results of parallel link experiments between such modules with both VCSELs and LEDs as sources will be shown. A large scale parallel bit error rate experiment at 90 Mbit/s/channel between two half-populated VCSEL-based FPGA modules with 112 of their 128 channels operational at bit error rates below 10-13 on all active channels (approximately equals 10 Gbit/s/chip) proves the feasibility of this approach. We first briefly discuss the general architecture and the realization of the optoelectronic FPGA demonstrator system. We then present measurement results on the available modules, followed by some conclusions on this work.

Two-dimensional optical interconnect between CMOS IC's

The central issue of optically interconnected integrated circuits (OIIC) concerns the area optical interconnect approach to the interconnect bottleneck encountered in advanced VLSI-CMOS designs. The envisaged route to solving this problem offers throughput data interconnects on inter-chip and MCM level, facilitating implementation of new digital architectures and systems. The OIIC project is aimed towards the realisation of three demonstrators: a system demonstrator, implementing state-of-the-art technology, and two link demonstrators, aiming at a high speed approach with 16 channels (Gigalink), and a low power, high density approach on 100 pm pitch with 100 channels (Photonlink). In the paper, progress and results in the project on architecture, components, optical pathways and mounting techniques for the system demonstrator will be highlighted. This system demonstrator aims at using a smart-pixel like interconnect structure to create a logically 3-D architecture, conceptually consisting of a number of electronic planes (electrical FPGAs), that are interconnected bidirectionally along a regular pattern that runs across the chip surface. The full-custom CMOS FPGA circuit is an 8/spl times/8 array of simple configurable logic blocks (a 4-bit function table, one flip-flop), interconnected by a programmable 6-6 switch matrix fabric, including the access to off-chip optical interconnections. The optical components consist of two 8/spl times/8 source arrays (either LEDs or VCSELs) and two 8/spl times/8 InP detector arrays, which are flip-chip bonded to the CMOS circuit and actually overlay part of the CMOS circuits. Electronic driving and receiving circuits are realised in CMOS, and are intermixed with the digital circuits. Each of the 256 optical channels is designed to operate at an information rate of 80 Mbit/s. To ensure reliable communication over so many parallel channels in a noisy digital environment, AC-coupled communication with Manchester coded data is used in the design. The optical pathways between the central chip and its two neighbours consists of removable 8/spl times/16 POF ribbons. Preliminary tests of the CMOS functionality have been completed with good results. A methodology for hybrid assembly, packaging and passive alignment of all components has been implemented. The hybridisation and packaging steps of the CMOS chips and the optical components, final assembly and measurements are discussed.

8/spl times/8 POF based interchip interconnection with 2.5 Gbit/s per channel data transmission

An optical 8/spl times/8 interchip interconnect with 2.5 Gbit/s-per-channel data transmission over a length of 50 cm is demonstrated. The interconnection approach is based on 125 /spl mu/m-plastic optical fibres (POF) which are aligned at a pitch of 250 /spl mu/m in two dimensions by precision plastic parts.

Demonstration of 2-D plastic optical fibre based optical interconnect between CMOS ICs

The design and fabrication of a digital system demonstrator implementing 2D optical interconnect via a POF ribbon are discussed. This demonstrator implements 256 optical I/O channels per chip. Each chip, a custom FPGA CMOS design, implements digital and analogue functionality.

Demonstrating POF based optoelectronic interconnect in a multi-FPGA prototype system

The goal of our work is demonstrating the viability of massively parallel optical interconnect between electronic CMOS VLSI chips. Here we describe the definition and realisation of a systems architecture in which these interconnections can play a meaningful role. The architecture is a multi-FPGA system with low level optoelectronic interconnects introduced into the FPGA chips. A demonstrator, reaching 10 Gbit/s/chip aggregate bit rate with small-scale custom made optoelectronic FPGAs, shows the feasibility of this approach.

A multi-FPGA demonstrator with POF-based optical area interconnect

It is our goal to demonstrate the viability of massively parallel optical interconnects between electronic VLSI chips. This is done through the development of the technology necessary for the realisation of such interconnections, and the definition and realisation of a systems architecture in which these interconnections play a meaningful role. Multi-FPGA systems have been identified as a good candidate for the introduction of low level optoelectronic interconnects, from both the systems and the purely demonstrator related points of view. An optoelectronic FPGA demonstrator along these lines is currently being realised. This involves besides the actual CMOS FPGA, the design and implementation of various light sources and detectors, as well as the analogue CMOS interface circuits; the building blocks of the optical pathways, which are based upon plastic optical fibre; and the methodology for hybrid assembly, packaging and passive alignment of all components. The optoelectronic FPGA demonstrator aims at using a smart-pixel like interconnect structure to create a logically 3-dimensional architecture.

Optical area I/O enhanced FPGA with 256 optical channels per chip

It is our goal to demonstrate the viability of massively parallel optical interconnections between electronic VLSI chips. This is done through the development of the technology necessary for the realization of such interconnections, and the definition of a systems architecture in which these interconnections play a meaningful role. Field-programmable gate arrays (FPGA) have been identified as a class of general-purpose very large scale integration components that could benefit from the massive introduction of state-of-the-art optical inter-chip interconnections at the logic level. In this paper, we present the realization of a small-scale optoelectronic FPGA with 8 X 8 logic cells, containing two optical sources and two receivers per FPGA cell yielding a total of 256 links per chip. These FPGA chips designed to operate with information rates of 80 Mbit/s/link will be used in a three- chip demonstrator system as a test bed for the concepts above. We first identify the reason why we think optical interconnects can provide added value in FPGAs. The next sections briefly discuss the general architecture of our demonstrator system and the realization of the optoelectronic FPGA. We then present first measurement results followed by ongoing work and conclusions.

64-channel two-dimensional POF-based optical array interchip interconnect

A 64 channel optical array interconnect based on 125 micrometers polymer optical fibers arranged in an 8 X 8 array with dimensions of 2 X 2 mm2 is presented. Typical insertion losses of 1.5 dB (660 nm) and 5 dB (980 nm) over 20 cm interconnection length have been measured.

2-dimensional fiber-based optical interconnect between CMOS IC's

Summary form only given. The increasing CMOS-IC complexity in terms of chip size, number of I/O pads and clock frequency poses more and more stringent problems for the system designer to solve, among which the interconnection problems, latency issues and power dissipation of the chips. Optical I/O over the entire chip area is pursued as a possible solution to the interconnection problems in the European Community funded ESPRIT project OIIC (optically interconnected integrated circuits). In this approach, data transfer from the whole chip area is facilitated through two-dimensional arrays of optical channels, consisting of opto-electronic components flip-chip mounted on CMOS circuitry and aligned to passive optical pathways.